5 research outputs found

    Acceleration of Spiking Neural Networks on Multicore Architectures

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    The human cortex is the seat of learning and cognition. Biological scale implementations of cortical models have the potential to provide significantly more power problem solving capabilities than traditional computing algorithms. The large scale implementation and design of these models has attracted significant attention recently. High performance implementations of the models are needed to enable such large scale designs. This thesis examines the acceleration of the spiking neural network class of cortical models on several modern multicore processors. These include the Izhikevich, Wilson, Morris-Lecar, and Hodgkin-Huxley models. The architectures examined are the STI Cell, Sun UltraSPARC T2+, and Intel Xeon E5345. Results indicate that these modern multicore processors can provide significant speed-ups and thus are useful in developing large scale cortical models. The models are then implemented on a 50 TeraFLOPS 336 node PlayStation 3 cluster. Results indicate that the models scale well on this cluster and can emulate 108 neurons and 1010 synapses. These numbers are comparable to the large scale cortical model implementation studies performed by IBM using the Blue Gene/L supercomputer. This study indicates that a cluster of PlayStation 3s can provide an economical, yet powerful, platform for simulating large scale biological models

    Implementación y Operación de un Cluster HPC utilizando Laboratorios de Computadoras en Horarios de Inactividad

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    This paper presents a preliminary report of a platform to facilitate students, teachers and researchers access HPC clusters at affordable costs using existing resources in institutions where They perform their activities. The computer labs of the universities constitute a reservoir of processing power. These can be used to form a cluster of high performance calculation in schedules that are not They find busy. In this way you can reduce the costs of owning an HPC cluster, expand the range of services and possibilities that the institution provides to its members and increase the use of laboratories improving its amortization and therefore justifying the investment better.Este trabajo presenta un reporte preliminar de una plataforma para facilitar a alumnos, docentes e investigadores el acceso a clusters HPC a costos accesibles utilizando recursos existentes en las instituciones donde desempeñan sus actividades. Los laboratorios de informática de las universidades constituyen un reservorio de potencia de procesamiento.  Estos pueden ser utilizados para conformar un cluster de cálculo de alto desempeño en los horarios que no se encuentran ocupados. De esta manera se puede al mismo tiempo reducir los costos de poseer un cluster HPC, ampliar el abanico de servicios y posibilidades que la institución brinda a sus miembros y aumentar la utilización de los laboratorios mejorando su amortización y por ende justificando mejor la inversión

    Ultra-Low Power IoT Smart Visual Sensing Devices for Always-ON Applications

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    This work presents the design of a Smart Ultra-Low Power visual sensor architecture that couples together an ultra-low power event-based image sensor with a parallel and power-optimized digital architecture for data processing. By means of mixed-signal circuits, the imager generates a stream of address events after the extraction and binarization of spatial gradients. When targeting monitoring applications, the sensing and processing energy costs can be reduced by two orders of magnitude thanks to either the mixed-signal imaging technology, the event-based data compression and the use of event-driven computing approaches. From a system-level point of view, a context-aware power management scheme is enabled by means of a power-optimized sensor peripheral block, that requests the processor activation only when a relevant information is detected within the focal plane of the imager. When targeting a smart visual node for triggering purpose, the event-driven approach brings a 10x power reduction with respect to other presented visual systems, while leading to comparable results in terms of detection accuracy. To further enhance the recognition capabilities of the smart camera system, this work introduces the concept of event-based binarized neural networks. By coupling together the theory of binarized neural networks and focal-plane processing, a 17.8% energy reduction is demonstrated on a real-world data classification with a performance drop of 3% with respect to a baseline system featuring commercial visual sensors and a Binary Neural Network engine. Moreover, if coupling the BNN engine with the event-driven triggering detection flow, the average power consumption can be as low as the sleep power of 0.3mW in case of infrequent events, which is 8x lower than a smart camera system featuring a commercial RGB imager
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