Network performance optimization using Odd and Even routing algorithm

The revolution on static wireless sensor network (WSN) had gained popularity in remote monitoring especially in oil and gas pipeline integrity. The use of WSN in oil and gas pipelines facilitates real time data transmission from sensors to the monitoring station located miles away. WSN for pipeline network are critical performance driven communication mechanism due to its unique linear geographical set up. The network performance of linear topology is compromised proportionally to the number of nodes. Such a drawback results in poor delivery ratio, throughput, latency and fairness due to its snowball effect towards the destination node. In this paper, we proposed a novel routing method, Odd-Even Linear Static Routing Path (OE-LSRP) to achieve significant improvements in overall network performance in TCP traffic. Various simulation experiments are tested with OE-LSRP in accordance to IEEE 802.11standard to achieve results in making it feasible for the pipeline network

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

TCP Timeout Mechanism for Optimization of Network Fairness and Performance in Multi-Hop Pipeline Network

In the recent years, wireless sensor network (WSN) has a huge impact in many remote based applications especially in oil and gas pipeline monitoring. Thus, the deployment of a multi-hop linear WSN will be a practical solution on pipelines. With a large multi-hop linear WSN, the overall network performance is badly affected especially due to node starvation. Inequality among source nodes is relatively an amplified factor of generated data rate and source node distances from the destination node. In this paper, we proposed a mathematical model for TCP Delayed Timeout Acknowledgement (DTO-ACK) mechanism for non-zero passive nodes. Optimum throughput fairness can be achieved by implementation of DTO-ACK with Dual Interleaving Linear Static Routing Protocol (DI-LSRP) for flat topology. Implementation of DTO-ACK and modification of TCP parameters reduces packet collision and ensures optimal throughput fairness in a multi-hop linear topology using TCP agent

A Scalable and Adaptive Network on Chip for Many-Core Architectures

In this work, a scalable network on chip (NoC) for future many-core architectures is proposed and investigated. It supports different QoS mechanisms to ensure predictable communication. Self-optimization is introduced to adapt the energy footprint and the performance of the network to the communication requirements. A fault tolerance concept allows to deal with permanent errors. Moreover, a template-based automated evaluation and design methodology and a synthesis flow for NoCs is introduced

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on Multiprocessor System on a Chip (MPSoC). However, the design of efficient NoC fabric with high performance is critically complex because of its architectural parameters. Identifying a suitable scheduling algorithm to resolve arbitration among ports to obtain high-speed data transfer in the router is one of the most significant phases while designing a Network on chip based Multiprocessor System on a Chip. Low latency, throughput, space utilization, energy consumption, and reliability for Network on chip fabric are all determined by the router. The performance of the NoC system is hampered by the deadlock issues that plague conventional routing algorithms. This work develops a novel routing algorithm to address the deadlock problem. In this paper, a deterministic shortest path deadlock-free routing method is developed based on the analysis of the Turn Model. In the 2D-mesh structure, the algorithm uses separate routing methods for the odd and even columns. This minimizes the number of paths for a single channel, congestion, and latency. Two test scenarios—one with and one without a load test—were used to evaluate the proposed model. For a zero-load network, three clock cycles are utilized to transfer the packets. For the load network, five clocks are utilized to transfer the packets. The latency is measured for both cases without load and with load test and the corresponding latency is 3ns and 7ns respectively.The proposed method has an 18.57Mbps throughput.  The area and power utilization for the proposed method are 69% (IO utilization) and 0.128W respectively. In order to validate the proposed method, the latency is compared with existing work and 50% latency is reduced both with and without congestion load

Broadcasting in Noisy Radio Networks

The widely-studied radio network model [Chlamtac and Kutten, 1985] is a graph-based description that captures the inherent impact of collisions in wireless communication. In this model, the strong assumption is made that node $v$ receives a message from a neighbor if and only if exactly one of its neighbors broadcasts. We relax this assumption by introducing a new noisy radio network model in which random faults occur at senders or receivers. Specifically, for a constant noise parameter $p \in [0,1)$, either every sender has probability $p$ of transmitting noise or every receiver of a single transmission in its neighborhood has probability $p$ of receiving noise. We first study single-message broadcast algorithms in noisy radio networks and show that the Decay algorithm [Bar-Yehuda et al., 1992] remains robust in the noisy model while the diameter-linear algorithm of Gasieniec et al., 2007 does not. We give a modified version of the algorithm of Gasieniec et al., 2007 that is robust to sender and receiver faults, and extend both this modified algorithm and the Decay algorithm to robust multi-message broadcast algorithms. We next investigate the extent to which (network) coding improves throughput in noisy radio networks. We address the previously perplexing result of Alon et al. 2014 that worst case coding throughput is no better than worst case routing throughput up to constants: we show that the worst case throughput performance of coding is, in fact, superior to that of routing -- by a $\Theta(\log(n))$ gap -- provided receiver faults are introduced. However, we show that any coding or routing scheme for the noiseless setting can be transformed to be robust to sender faults with only a constant throughput overhead. These transformations imply that the results of Alon et al., 2014 carry over to noisy radio networks with sender faults.Comment: Principles of Distributed Computing 201