Energy-efficient resource allocation for edge computing based on models of power consumption

Computing services, when provided by Edge Networks rather than centralized clouds, are delivered close to the geographically extreme user edge. Edge computing enables functional offloading and improved scalability but suboptimal design of edge networks can result in needlessly high energy consumption and mismanagement of resources. Thus, how to effectively minimize the power dissipation of network resources at the edge is a significant problem as networks evolve. This thesis investigates a complete suite of energy efficient solution for the edge network. A frequency scalable router architecture, based on the Software Defined Network (SDN) concept, has been proposed. Two new control policies have been integrated with the proposed green architecture and their performance has been analysed to evaluate the trade-offs between energy efficiency and performance in frequency-scaled Network Devices. A Network Device Power Model (NDPM) has been formulated to explore the power dissipation characteristics of frequency scalable CMOS devices (as measured using a NetFPGA testbed). An Online Energy-efficient Resource Allocation model (OERA) has been designed based on this model. This allocation model can map the resource requests onto a substrate network in the edge, with concurrent consideration of multiple factors including geographical location, resource availability and network-level energy cost, etc. The model features better support of virtual resource requests and lower power consumption than existing solutions

An FPGA-based network system with service-uninterrupted remote functional update

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption

Encaminhamento por Hardware em Redes Definidas por Software: Avaliação Experimental Utilizando NETFPGA

As redes de computadores se tornaram parte essencial da infraestrutura de nossa sociedade, no entanto, o projeto inicial das redes tradicionais não poderia atender os requisitos de todas essas aplicações, pois muitas não foram sequer imaginadas. Como resultado, tem-se um ambiente de redes com pouco suporte e flexibilidade para anteder às novas exigências. Nesse contexto, surgiu, então, um conceito promissor de redes programáveis denominado Redes Definidas por Software (SDN Software Defined Network). SDN separa o plano de controle do plano de dados permitindo aos desenvolvedores programar a rede de acordo com as necessidades de suas aplicações. Além disso, tornou possível a implementação e testes em ambientes reais, inovações tecnológicas para o ambiente de redes sem, para isso, depender dos fabricantes de equipamentos. Este trabalho propõe a utilização de NetFPGAs como ferramenta de encaminhamento em SDN, controlada por um controlador OpenFlow a fim de diminuir o caminho percorrido por um pacote de sua origem ao seu destino. Além disso, propõese utilizar a NetFPGA com OpenFlow para uma implementação de múltiplos caminhos com balanceamento de cargas. Será avaliada, ainda, a influência de tabelas de fluxos na comutação de pacotes comparando um protocolo que utiliza tabelas para encaminhamento (OpenFlow) com um que não utiliza tabelas para este fim (KeyFlow)

Projeto, implementaçâo e avaliação de um gateway de rede de banda larga usando um processador de pacote programável

Orientador: Christian Rodolfo Esteve RothenbergDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: BNG, também conhecido como BRAS desempenha um papel crucial na Internet atual, ele maneja a maioria do tráfego da rede de acesso, implementando políticas e serviços que um Internet Service Provider (ISP) define por assinante. Porém, este dispositivo de rede é caro, proprietário, limitado e de lenta atualização, virando um ponto de falha para implantar novas funcionalidades e corrigir problemas na rede sem interromper a operação normal do serviço. Este trabalho pretende projetar, implementar e evaluar um BNG S/W switch flexível e otimizado usando a linguagem P4, aproveitando seus recursos para descrever o processamento de pacotes com programação de plano de dados agnóstica ao alvo que é vantajoso ao fornecer aos desenvolvedores (por exemplo, operadores de rede) uma alternativa aos esquemas de manipulação de pacotes. Nos propomos usar o compilador MACSAD que junta a abstração de P4 e APIs de OpenDataPlane (ODP) para suportar aplicativos de rede baseados em Linux com alto desempenho em varias arquiteturas (ARM, Intel, MIPS e PowerPC). A versão atual do MACSAD dá suporte para a versão anterior da linguagem P4 (P4 _14). Portanto, parte deste trabalho é dar suporte ao compilador MACSAD para o versão atual (P4 _16) no qual é construído o plano de dados de BNG. Além disso, foi feita uma avaliação funcional e de desempenho do BNG S/W switch em um cenário realista e usando dois geradores de tráfego Open Source em H/W e S/W. Os resultados mostram o impacto dos parâmetros do dispositivo alvo, tais como o número de núcleos, tamanhos de burst, pacotes de E/S e cargas de trabalho que afetam o desempenho em termos de taxa de transferência e latência fornecendo os melhores parametros de configuração para nossa implementaçãoAbstract: Broadband Network Gateway (BNG), also known as Broadband Remote Access Server (BRAS) plays a crucial role in today¿s internet, as it handles the majority of access network traffic, implementing network policies and services that a Internet Service Provider (ISP) defines per subscriber. However, this network device is normally expensive, proprietary, limited and slow to upgrade, and a point of failure when deploying new functionalities and correcing issues on the network without disrupting normal service operations. This work intends to design, implement and evaluate a flexible and optimized BNG Software (S/W) switch by using programming protocol-independent packet processors (P4) language, taking advantage of its features to describe the packet processing with target-agnostic data-plane programmability which is advantageous by providing to developers (i.e., network operators) an alternative to packet handling schemes. We propose to use the Multi-Architecture Compiler System for Abstract Dataplanes (MACSAD) compiler which merges the P4 abstraction and OpenDataPlane (ODP) APIs to support Linux-based network applications with high performance across some architectures (ARM, Intel, MIPS, and PowerPC). The actual version of MACSAD brings support for the previous release of the P4 language (P4_14). Therefore part of this work is to bring support to MACSAD for the current release (P4_16) on which the proposed BNG dataplane is built. We use functional and performance evaluation of the BNG S/W switch in a realistic scenario rs. The results show the impact of both target parameters such as the number of cores, burst sizes, packet IO, and workloads and how it affects the performance regarding throughput and latency bringing the best parameter configuration for our implementationMestradoEngenharia de ComputaçãoMestre em Engenharia Elétric

Progressive Network Deployment, Performance, and Control with Software-defined Networking

The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or shim could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in latency, showing that such a solution may be feasible. It is hypothesized that a new design built on event-loop and reactive programming may yield a controller that is higher-performing and easier to program. The library node-openflow is found to have performance approaching that of professional controllers, however it exhibits higher variability in response rate. The framework rxdn is found to exceed performance of two comparable controllers by at least 33% with statistical significance in latency mode with 16 simulated switches, but is slower than the library node-openflow or professional controllers (e.g., Libfluid, ONOS, and NOX). Collectively, this work enhances the tools available to researchers, enabling experimentation and development toward more sustainable and secure infrastructur

Fast Packet Processing on High Performance Architectures

The rapid growth of Internet and the fast emergence of new network applications have brought great challenges and complex issues in deploying high-speed and QoS guaranteed IP network. For this reason packet classication and network intrusion detection have assumed a key role in modern communication networks in order to provide Qos and security. In this thesis we describe a number of the most advanced solutions to these tasks. We introduce NetFPGA and Network Processors as reference platforms both for the design and the implementation of the solutions and algorithms described in this thesis. The rise in links capacity reduces the time available to network devices for packet processing. For this reason, we show different solutions which, either by heuristic and randomization or by smart construction of state machine, allow IP lookup, packet classification and deep packet inspection to be fast in real devices based on high speed platforms such as NetFPGA or Network Processors

Securing Network Processors with Hardware Monitors

As an essential part of modern society, the Internet has fundamentally changed our lives during the last decade. Novel applications and technologies, such as online shopping, social networking, cloud computing, mobile networking, etc, have sprung up at an astonishing pace. These technologies not only influence modern life styles but also impact Internet infrastructure. Numerous new network applications and services require better programmability and flexibility for network devices, such as routers and switches. Since traditional fixed function network routers based on application specific integrated circuits (ASICs) have difficulty keeping pace with the growing demands of next-generation Internet applications, there is an ongoing shift in the industry toward implementing network devices using programmable network processors (NPs). While network processors offer great benefits in terms of flexibility, their reprogrammable nature exposes potential security risks. Similar to network end-systems, such as general-purpose computers, software-based network processors have security vulnerabilities that can be attacked remotely. Recent research has shown that a new type of data plane attack is able to modify the functionality of a network processor and cause a denial-of-service (DoS) attack by sending a single malformed UDP packet. Since this attack relies solely on data plane access and does not need access to the control plane, it can be particularly difficult to control. Hardware security monitors have been introduced to identify and eliminate these malicious packets before they can propagate and cause devastating effects in the network. However, previous work on hardware monitors only focus on single core systems with static (or very slowly changing) workloads. In network processors that use up to hundreds of parallel processor cores and have processing workloads that can change dynamically based on the network traffic, the realization of a complete multicore hardware monitoring system remains a critical challenge. Our research work in this thesis provides a comprehensive solution to this problem. Our first contribution is the design and prototype implementation of a Scalable Hardware Monitoring Grid (SHMG). This scalable architecture balances area cost and performance overhead by using a clustered approach for multicore NP systems. In order to adapt to dynamically changing network traffic, a resource reallocation algorithm is designed to reassign the processing resources in SHMG to different network applications at runtime. An evaluation of the prototype SHMG on an Altera DE4 board demonstrates low resource and performance overheads. The functionality and performance of a runtime resource reallocation algorithm are tested using a simulation environment. A second significant contribution of this work is a network system-level security solution for multicore network processors with hardware monitors. It addresses two key problems: (1) how to securely manage and reprogram processor cores and monitors in a deployed router in the network, and (2) how to prevent the large number of identical router devices in the network from an attack that can circumvent one specific monitoring system and lead to Internet-scale failures. A Secure Dynamic Multicore Hardware Monitoring System (SDMMon) is designed based on cryptographic principles and suitable key management to ensure the secure installation of processor binaries and monitor graphs. We present a Merkle tree based parameterizable high performance hash function that can be configured to perform a variety of functions in different devices via a 32-bit configuration parameter. A prototype system composed of both the SDMMon and the parameterizable hash is implemented and evaluated on an Altera DE4 board. Finally, a fully-functional, comprehensive Multicore NP Security Platform, which integrates both the SHMG and the SDMMon security features, has been implemented on an Altera DE5 board

Transmission haut-débit sur les réseaux d'énergie: principes physiques et compatibilité électromagnétique

Power Line Communications consist of transmitting data by reusing the existing powerline as a propagation medium. Powerline networks represent a challenging environment for broadband communications, since they have not been designed for the transmission of high frequency signals. This Habilitation degree thesis presents our research on transmission physics and electromagnetic compatibility for in-home powerline networks. This research has been conducted since 2007 in the framework of a collaboration between Orange Labs and Telecom Bretagne, involving my supervision of three Ph.D. theses defended in 2012, 2013 and 2015, as the principal advisor.La technologie Courant Porteur en Ligne consiste à transmettre des données en réutilisant le réseau électrique classique en tant que support de propagation. Les réseaux d'énergie sont des environnements difficiles pour les communications à haut débit, car ils n'ont pas été conçus pour la transmission d'un signal à haute fréquence. Ce mémoire d'Habilitation à Diriger des Recherches présente mes travaux concernant la physique de la transmission et les aspects de Compatibilité Electro-Magnétique (CEM) pour le réseau électrique domestique. Ils ont été réalisés à partir de 2007 dans le cadre d'une collaboration entre Orange Labs et Telecom Bretagne, notamment à travers trois thèses soutenues en 2012, 2013 et 2015. Après une introduction générale à la technologie CPL, le manuscrit décrit l'environnement de propagation dans les réseaux d'énergie en termes de canal et de bruit électromagnétique. Les principes de la modélisation du canal CPL sont illustrés à partir de la problématique d'identification des trajets de propagation. L'une des principales évolutions du domaine concerne l'application de la technologie Multiple Input Multiple Output (MIMO) aux communications sur réseaux d'énergie. Nos études expérimentales ont démontré que l'adaptation de cette technique issue du domaine de la radio permet un doublement de la capacité de transmission. Nous présentons les campagnes de mesure réalisées au sein d'Orange Labs et du groupe Specialist Task Force 410 de l'ETSI. A partir de ces données, des modèles statistiques de canal de propagation MIMO et de bruit multi-capteurs ont été élaborés. En termes d'émission électromagnétique, la bande utilisée par les systèmes CPL est déjà occupée par d'autres services (radio amateur, radiodiffusion en ondes courtes). Nous décrivons les contraintes CEM des systèmes CPL et abordons les techniques de CEM cognitive, consistant à optimiser les ressources spectrales en tenant compte de la connaissance de l'environnement du système. En particulier, la technique de retournement temporel est étudiée pour la mitigation du rayonnement involontaire et sa performance est étudiée de manière expérimentale. Enfin, le manuscrit présente la problématique de l'efficacité énergétique des systèmes CPL. Nous présentons les mesures expérimentales réalisées afin de modéliser la consommation de modems classiques et MIMO. D'autre part, la configuration de communication en relais a été étudiée, afin d'évaluer le gain de ce mode de transmission en termes de consommation énergétique. A l'avenir, ces travaux pourront être étendus aux réseaux de distribution en basse et moyenne tension, pour le développement et l'optimisation des réseaux d'énergie intelligents, ou Smart Grids

Journal of Telecommunications and Information Technology, nr 3

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