Ethernet - a survey on its fields of application

During the last decades, Ethernet progressively became the most widely used local area networking (LAN) technology. Apart from LAN installations, Ethernet became also attractive for many other fields of application, ranging from industry to avionics, telecommunication, and multimedia. The expanded application of this technology is mainly due to its significant assets like reduced cost, backward-compatibility, flexibility, and expandability. However, this new trend raises some problems concerning the services of the protocol and the requirements for each application. Therefore, specific adaptations prove essential to integrate this communication technology in each field of application. Our primary objective is to show how Ethernet has been enhanced to comply with the specific requirements of several application fields, particularly in transport, embedded and multimedia contexts. The paper first describes the common Ethernet LAN technology and highlights its main features. It reviews the most important specific Ethernet versions with respect to each application field’s requirements. Finally, we compare these different fields of application and we particularly focus on the fundamental concepts and the quality of service capabilities of each proposal

Simulation of Mixed Critical In-vehicular Networks

Future automotive applications ranging from advanced driver assistance to autonomous driving will largely increase demands on in-vehicular networks. Data flows of high bandwidth or low latency requirements, but in particular many additional communication relations will introduce a new level of complexity to the in-car communication system. It is expected that future communication backbones which interconnect sensors and actuators with ECU in cars will be built on Ethernet technologies. However, signalling from different application domains demands for network services of tailored attributes, including real-time transmission protocols as defined in the TSN Ethernet extensions. These QoS constraints will increase network complexity even further. Event-based simulation is a key technology to master the challenges of an in-car network design. This chapter introduces the domain-specific aspects and simulation models for in-vehicular networks and presents an overview of the car-centric network design process. Starting from a domain specific description language, we cover the corresponding simulation models with their workflows and apply our approach to a related case study for an in-car network of a premium car

VEGa : a high performance vehicular Ethernet gateway on hybrid FPGA

Modern vehicles employ a large amount of distributed computation and require the underlying communication scheme to provide high bandwidth and low latency. Existing communication protocols like Controller Area Network (CAN) and FlexRay do not provide the required bandwidth, paving the way for adoption of Ethernet as the next generation network backbone for in-vehicle systems. Ethernet would co-exist with safety-critical communication on legacy networks, providing a scalable platform for evolving vehicular systems. This requires a high-performance network gateway that can simultaneously handle high bandwidth, low latency, and isolation; features that are not achievable with traditional processor based gateway implementations. We present VEGa, a configurable vehicular Ethernet gateway architecture utilising a hybrid FPGA to closely couple software control on a processor with dedicated switching circuit on the reconfigurable fabric. The fabric implements isolated interface ports and an accelerated routing mechanism, which can be controlled and monitored from software. Further, reconfigurability enables the switching behaviour to be altered at run-time under software control, while the configurable architecture allows easy adaptation to different vehicular architectures using high-level parameter settings. We demonstrate the architecture on the Xilinx Zynq platform and evaluate the bandwidth, latency, and isolation using extensive tests in hardware

Tunneling Horizontal IEC 61850 Traffic through Audio Video Bridging Streams for Flexible Microgrid Control and Protection

In this paper, it is argued that some low-level aspects of the usual IEC 61850 mapping to Ethernet are not well suited to microgrids due to their dynamic nature and geographical distribution as compared to substations. It is proposed that the integration of IEEE time-sensitive networking (TSN) concepts (which are currently implemented as audio video bridging (AVB) technologies) within an IEC 61850 / Manufacturing Message Specification framework provides a flexible and reconfigurable platform capable of overcoming such issues. A prototype test platform and bump-in-the-wire device for tunneling horizontal traffic through AVB are described. Experimental results are presented for sending IEC 61850 GOOSE (generic object oriented substation events) and SV (sampled values) messages through AVB tunnels. The obtained results verify that IEC 61850 event and sampled data may be reliably transported within the proposed framework with very low latency, even over a congested network. It is argued that since AVB streams can be flexibly configured from one or more central locations, and bandwidth reserved for their data ensuring predictability of delivery, this gives a solution which seems significantly more reliable than a pure MMS-based solution

Pre-Shaping Bursty Transmissions under IEEE802.1Q as a Simple and Efficient QoS Mechanism

International audienceThe automotive industry is swiftly moving towards Ethernet as the high-speed communication network for in-vehicle communication. There is nonetheless a need for protocols that go beyond what standard Ethernet has to offer in order to provide additional QoS to demanding applications such as ADAS systems or audio/video streaming. The main protocols currently considered for that purpose are IEEE802.1Q, AVB with the Credit Based Shaper mechanism (IEEE802.1Qav) and TSN with its Time-Aware Shaper (IEEE802.1Qbv). AVB/CBS and TSN/TAS both provide efficient QoS mechanisms and they can be used in a combined manner, which offers many possibilities to the designer. Their use however requires dedicated hardware and software components, and clock synchronization in the case of TAS. Previous studies have also shown that the efficiency of these protocols depends much on the application at hand and the value of the configuration parameters. In this work, we explore the use of "pre-shaping" strategies under IEEE802.1Q for bursty traffic such as audio/video streams as a simple and efficient alternative to AVB/CBS and TSN/TAS. Pre-shaping means inserting on the sender side "well-chosen" pauses between successive frames of a burst (e.g., a camera frame), all the other characteristics of traffic remaining unchanged. We show on an automotive case-study how the use of pre-shaping for audio/video streams leads to a drastic reduction of the communication latencies for the best-effort streams while enabling to meet the timing constraints for the rest of the traffic. We then discuss the limitations of the pre-shaping mechanism and future works needed to facilitate its adoption

A real-time networked camera system:a scheduled distributed camera system reduces the latency

This report presents the results of a Real-time Networked Camera System, com-missioned by the SAN Group in TU/e. Distributed Systems are motivated by two reasons, the first reason is the physical environment as a requirement and the second reason is to provide a better Quality of Service (QoS). This project describes the distributed system with a video processing application. The aim is to deal with the distributed system as one system thus minimizing delays while keeping the predictability in a real-time context. Time is the most crucial ingredient for the real-time systems in the sense that the tasks within the application should meet with the task deadline. With respect to the distributed system we need to consider a couple of issues. The first one is to have a distributed system and a modular application that is mapped to multiple system nodes. The second issue is to schedule the modules collectively and the third is to propose a solution when shared resource(s) (such as the network) are required by several nodes at the same time. In order to provide a distributed system, we connect 2 cameras with 1 PC via a network switch. Video processing has two parts; the first part consists of creating a frame, encoding the frame, and streaming it to the network and the second part deals with receiving the frame, decoding the frame, and displaying the frame. The first part is running on the cameras and the second part is running on the PC. In order to give real-time behavior to the system, the system components should provide the real-time behavior. The camera is installed with the µC/OS-II (Open Source Real-time Kernel). We investigated the Real-time Operating System and its installation on the PC. In order to provide resource management to the shared resources, we designed and implemented Admission control which controls access to the required con-nection to the PC. We designed and implemented a component to delay the start of any of the cameras in order to synchronize the network utilization. We also designed an enforcement component to allow the tasks to run as much as they should and monitor the frames streamed to the network. The results show that with the Admission Control, cameras only send as many frames as the network can transport. The given start delay to the system shows that overlap can be prevented, but we could not evaluate it because of the semi-tested/unreleased code which is provided by the camera providers. The source code we used is the test source code which was not mature

High Performance Computing via High Level Synthesis

As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of the available computing power. This thesis is in particular devoted to High Performance Computing applications, where those trends are carried to the extreme. In this domain, the primary aspects to be taken into consideration are (1) performance (by definition) and (2) energy consumption (since operational costs dominate over procurement costs). These requirements can be satisfied more easily by deploying heterogeneous platforms, which include CPUs, GPUs and FPGAs to provide a broad range of performance and energy-per-operation choices. In particular, as we will see, FPGAs clearly dominate both CPUs and GPUs in terms of energy, and can provide comparable performance. An important aspect of this trend is of course design technology, because these applications were traditionally programmed in high-level languages, while FPGAs required low-level RTL design. The OpenCL (Open Computing Language) developed by the Khronos group enables developers to program CPU, GPU and recently FPGAs using functionally portable (but sadly not performance portable) source code which creates new possibilities and challenges both for research and industry. FPGAs have been always used for mid-size designs and ASIC prototyping thanks to their energy efficient and flexible hardware architecture, but their usage requires hardware design knowledge and laborious design cycles. Several approaches are developed and deployed to address this issue and shorten the gap between software and hardware in FPGA design flow, in order to enable FPGAs to capture a larger portion of the hardware acceleration market in data centers. Moreover, FPGAs usage in data centers is growing already, regardless of and in addition to their use as computational accelerators, because they can be used as high performance, low power and secure switches inside data-centers. High-Level Synthesis (HLS) is the methodology that enables designers to map their applications on FPGAs (and ASICs). It synthesizes parallel hardware from a model originally written C-based programming languages .e.g. C/C++, SystemC and OpenCL. Design space exploration of the variety of implementations that can be obtained from this C model is possible through wide range of optimization techniques and directives, e.g. to pipeline loops and partition memories into multiple banks, which guide RTL generation toward application dependent hardware and benefit designers from flexible parallel architecture of FPGAs. Model Based Design (MBD) is a high-level and visual process used to generate implementations that solve mathematical problems through a varied set of IP-blocks. MBD enables developers with different expertise, e.g. control theory, embedded software development, and hardware design to share a common design framework and contribute to a shared design using the same tool. Simulink, developed by MATLAB, is a model based design tool for simulation and development of complex dynamical systems. Moreover, Simulink embedded code generators can produce verified C/C++ and HDL code from the graphical model. This code can be used to program micro-controllers and FPGAs. This PhD thesis work presents a study using automatic code generator of Simulink to target Xilinx FPGAs using both HDL and C/C++ code to demonstrate capabilities and challenges of high-level synthesis process. To do so, firstly, digital signal processing unit of a real-time radar application is developed using Simulink blocks. Secondly, generated C based model was used for high level synthesis process and finally the implementation cost of HLS is compared to traditional HDL synthesis using Xilinx tool chain. Alternative to model based design approach, this work also presents an analysis on FPGA programming via high-level synthesis techniques for computationally intensive algorithms and demonstrates the importance of HLS by comparing performance-per-watt of GPUs(NVIDIA) and FPGAs(Xilinx) manufactured in the same node running standard OpenCL benchmarks. We conclude that generation of high quality RTL from OpenCL model requires stronger hardware background with respect to the MBD approach, however, the availability of a fast and broad design space exploration ability and portability of the OpenCL code, e.g. to CPUs and GPUs, motivates FPGA industry leaders to provide users with OpenCL software development environment which promises FPGA programming in CPU/GPU-like fashion. Our experiments, through extensive design space exploration(DSE), suggest that FPGAs have higher performance-per-watt with respect to two high-end GPUs manufactured in the same technology(28 nm). Moreover, FPGAs with more available resources and using a more modern process (20 nm) can outperform the tested GPUs while consuming much less power at the cost of more expensive devices

Reserva de recursos em automotive ethernet

Mestrado em Engenharia Electrónica e TelecomunicaçõesIn recent years, automotive industry has undergone major changes, being able to highlight not only the growing development of electronic systems in increasingly and varied features and contexts, as well as to cope with its growing interaction between with the driver and the outside world. Due to the huge amount of traffic involved in these system communications, networking technologies used so far are starting to be less appealing and the industry began to consider alternatives, economically more competitive as is the case of Ethernet. The use of Ethernet technology in automotive domains faces some challenges, namely with time constraints compliance and well defined resource requirements. The emergence of AVB (Audio Video Bridging) protocols, is trying to tackle some of these problems of having dynamic Quality of Service management in automotive Ethernet networks. One example of such protocols is the signalling protocol (SRP Stream Reservation Protocol), which could be used for providing a resource reservation mechanism in an automotive Ethernet domain. To test the feasibility of such recent methods, simulation tools are of paramount importance. This work presents an implementation of the SRP (Stream Reservation Protocol) in Omnet++, taking into account some of its constraints. It is described the fundamental aspects of this model implementation, as well as some functional tests.Nos últimos anos, a industria automóvel tem sofrido grandes evoluções, podendo-se destacar não só o crescente desenvolvimento de sistemas eletrónicos em contextos e funcionalidades cada vez mais variados, como também a crescente interacção deste com o condutor e o mundo exterior. Devido ao enorme aumento de tráfego envolvido nas comunicações que compõem esses sistemas, as tecnologias de redes usadas até então deixaram de ser tão apelativas e passaram-se a considerar alternativas económicamente mais competitivas como é o caso da Ethernet. O uso de redes Ethernet em âmbito automóvel levanta alguns problemas, nomeadamente no cumprimento de limites temporais e requisitos de recursos bem definidos. O aparecimento de protocolos AVB (Audio Video Bridging) vem tentar colmatar vários problemas de gestão dinâmica de Qualidade de Serviço das redes Ethernet no domínio automóvel. O protocol de sinalização SRP (Stream Reservation Protocol) pode ser adaptado para redes Ethernet no contexto automóvel para proporcionar um mecanismo de reserva de recursos. Para testar a viabilidade de métodos tão recentes, as ferramentes de simulação são de uma importância vital. Este trabalho apresententa uma implemetação do protocolo SRP (Stream Reservation Protocol) em ambiente de simulação OMNeT++. São apresentados os aspectos fundamentais do modelo implemetado bem como alguns testes funcionais de validação deste

Time-Sensitive Networking for Industrial Automation: Challenges, Opportunities, and Directions

With the introduction of Cyber-Physical Systems (CPS) and Internet of Things (IoT) into industrial applications, industrial automation is undergoing tremendous change, especially with regard to improving efficiency and reducing the cost of products. Industrial automation applications are often required to transmit time- and safety-critical data to monitor and control industrial processes, especially for critical control systems. There are a number of solutions to meet these requirements (e.g., priority-based real-time schedules and closed-loop feedback control systems). However, due to their different processing capabilities (e.g., in the end devices and network switches), different vendors may come out with distinct solutions, and this makes the large-scale integration of devices from different vendors difficult or impossible. IEEE 802.1 Time-Sensitive Networking (TSN) is a standardization group formed to enhance and optimize the IEEE 802.1 network standards, especially for Ethernet-based networks. These solutions can be evolved and adapted into a cross-industry scenario, such as a large-scale distributed industrial plant, which requires multiple industrial entities working collaboratively. This paper provides a comprehensive review on the current advances in TSN standards for industrial automation. We present the state-of-the-art IEEE TSN standards and discuss the opportunities and challenges when integrating each protocol into the industry domains. Finally, we discuss some promising research about applying the TSN technology to industrial automation applications