Modeling and control of single-stage quadratic-boost split source inverters

This paper aims to develop the recently introduced Spilt-Source Inverter (SSI) topology to improve its boosting characteristics. New SSI topologies with high voltage gain are introduced in this paper. The proposed converters square the basic SSI’s boosting factor by utilizing an additional inductor, capacitor, and two diodes. Thus, the proposed converters are called Quadratic-Boost (or Square-Boost) SSIs (QBIs or SBIs). Four different QBI topologies are presented. One with continuous input current (CC-QBI), and the other draws a discontinuous input current (DC-QBI) but with reduced capacitor voltage stresses. This paper also introduces the small-signal model of the CC-QBI using state variables perturbance. Based on this model, the closed-loop voltage and current control approach of the dc-boosting factor are designed. Moreover, a modified space vector modulation (MSVM) scheme is presented to reduce the input current ripples. To evaluate the performance of the proposed topologies, a comparative study between them and the other counterpart from different perspectives is introduced. It can be found that the CC-QBI topology has superior boosting characteristics when operating with low input voltage compared with their counterparts. It has a higher boosting capability, lower capacitor voltages, and semiconductor stresses, especially when high voltage gains are required. These merits make the proposed topologies convenient to the Photovoltaic and Fuel-Cell systems. Finally, the feasibility of the suggested topology and the introduced mathematical model is verified via simulation and experimental results, which show good accordance with the theoretical analysis. AuthorScopu

Characterizing and modeling methods for power converters

“Stable power delivery is becoming increasingly important in modern electronic devices, especially in applications with stringent requirements of its form factor. With the evolution of technology, the switching frequency in a power converter is pushed to a higher frequency range, e.g., several MHz or even higher, to decrease its size. However, the loss generated in the converter increases drastically due to the high switching frequency. In addition, a wide-band feedback controller is required to accommodate the high switching frequency in the converter. We focus on the characterization or modeling of the feedback control circuits and critical components in a switching power converter. A transient-simulation-oriented averaged continuous-time model is proposed to evaluate the transient output noise of a buck converter. The proposed modeling method is developed with time-domain waveforms, which enables a generalized modeling framework for current-mode controllers with constant and nonconstant switching frequencies. In this work, we mainly focus on characterization for two types of components: the switching components, including Si MOSFETs and GaN High-electron-mobility transistor (HEMT), and the magnetic core in an inductor. For the characterization of switching components, a set of test fixtures are designed to characterize the equivalent circuit of Si MOSFETs and GaN HEMTs. The frequency-dependent behaviors of Si MOSFETs are observed, which invalidate the conventional modeling methods for MOSFETs, especially for radiated emission (RE) prediction. For the characterization of magnetic cores, two different probe calibration methods are demonstrated. Accurate phase discrepancy characterization is allowed with the proposed method, which overcomes the main limitation in the conventional two-winding method. In addition, the proposed method supports wide-band loss measurement without resonance tuning, which supports core loss measurement for non-sinusoidal excitation”--Abstract, page iv

A Pipeline Analog-To-Digital Converter for a Plasma Impedance Probe

Space instrumentation technology is an essential tool for rocket and satellite research, and is expected to become popular in commercial and military operations in fields such as radar, imaging, and communications. These instruments are traditionally implemented on printed circuit boards using discrete general-purpose Analog-to-Digital Converter (ADC) devices and other components. A large circuit board is not convenient for use in micro-satellite deployments, where the total payload volume is limited to roughly one cubic foot. Because micro-satellites represent a fast growing trend in satellite research and development, there is motivation to explore miniaturized custom application-specific integrated circuit (ASIC) designs to reduce the volume and power consumption occupied by instrument electronics. In this thesis, a model of a new Plasma Impedance Probe (PIP) architecture, which utilizes a custom-built ADC along with other analog and digital components, is proposed. The model can be fully integrated to produce a low-power, miniaturized impedance probe

Factors Affecting Stable Operation of Grid-Connected Three-Phase Photovoltaic Inverters

The amount of grid-connected photovoltaic energy generation has grown enourmously since the beginning of the 21st century. Photovoltaic power plants are interfaced with the utility grid by using three or single-phase inverters which convert the direct current generated by the photovoltaic modules into three or single-phase alternating current. The photovoltaic inverters have been observed to degrade power quality in the grid and to suffer from reliability problems related to their control software. Therefore, the design of these inverters has become a significant research topic in academia and in the power electronic industry. Control design of a photovoltaic inverter is often based on the small-signal models characterizing its dynamic behavior. In this thesis, the existing small-signal models are upgraded to include the effect of an upstream DC-DC converter and its control mode. In addition, the models are upgraded to include the effect of a phase-locked-loop which is often used as a synchronization method and the effect of the grid-voltage feedforward which is often used to improve the transient performance. The control mode of the upstream DC-DC converter is shown to have a significant effect on the minimum DC-link capacitance which is required for stable operation due to a RHP-pole in the inverter control dynamics. However, operating the DC-DC converter under input-voltage control is shown to remove the RHP-pole and, consequently, the constraint imposed on the size of the minimum DC-link capacitance. The phase-locked-loop (PLL) is shown to make the q-component of the inverter’s output impedance resemble a negative resistor. Based on the small-signal models, the negative resistance is shown to appear at the frequencies below the crossover frequency of the PLL. Therefore, a wide-bandwidth PLL causes easily instability due to the negative-resistance behavior when the grid inductance is large. The grid-voltage feedforward is shown to increase the magnitude of both the d and q-components of the inverter’s output impedance. The PV inverter with grid-voltage feedforward is shown to be more resistant against impedance-based interactions than an inverter without the feedforward

Development of the Readout Electronics for the Beam Loss Monitors of the LHC

The Large Hadron Collider (LHC) of the European Laboratory for Particle Physics will be the largest particle accelerator in the world. It requires a large number of installations for its operation. One of these installations are the beam loss monitors which measure the particle losses. If these losses exceed a certain level, the beam must be extracted, otherwise the superconducting magnets could be damaged. For this reason, ionization chambers are installed outside the cryostat to transform the losses into an electric current. A wide dynamic range front end was developed to measure this current. The circuit consists of a current-to-frequency converter that works on the principle of balanced charge. Its output frequency is evaluated by counters and the data is serially transmitted from the tunnel to the surface, where the final data processing is performed. The data transmission suffers from the long cabling distance of up to 2 km. Using Manchester Code and line equalizers enables a data rate of 2 Mbit/s over a common twisted pair cable. This transmission problems lead to a detailed analysis of transmission lines in the frequency and time domain

Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented