297 research outputs found

    Novel dual-threshold voltage FinFETs for circuit design and optimization

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    A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology

    Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits

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    This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology

    Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

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    Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

    Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications

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    Continuous scaling of CMOS technology has now reached a state of evolution, therefore, novel device structures and new materials have been proposed for this purpose. The Screen- Grid field Effect Transistor is introduced as a as a novel device structure that takes advantage of several innovative aspects of the FinFET while introducing new geometrical feature to improve a FET device performance. The idea is to design a FET which is as small as possible without down-scaling issues, at the same time satisfying optimum device performance for both analogue and digital applications. The analogue operation of the SGrFET shows some promising results which make it interesting to continue the investigation on SGrFET for digital applications. The SGrFET addresses some of the concerns of scaled CMOS such as Drain Induce Barrier Lowering and sub-threshold slope, by offering the superior short channel control. In this work in order to evaluate SGrFET performance, the proposed device compared to the classical MOSFET and provides comprehensive benchmarking with finFETs. Both AC and DC simulations are presented using TaurusTM and MediciTM simulators which are commercially available via Synopsis. Initial investigation on the novel device with the single gate structure is carried out. The multi-geometrical characteristic of the proposed device is used to reduce parasitic capacitance and increase ION/IOFF ratio to improve device performance in terms of switching characteristic in different circuit structures. Using TaurusTM AC simulation, a small signal circuit is introduced for SGrFET and evaluated using both extracted small signal elements from TaurusTM and Y-parameter extraction. The SGrFET allows for the unique behavioural characteristics of an independent-gate device. Different configurations of double-gate device are introduced and benchmark against the finFET serving as a double gate device. Five different logic circuits, the complementary and N-inverter, the NOR, NAND and XOR, and controllable Current Mirror circuits are simulated with finFET and SGrFET and their performance compared. Some digital key merits are extracted for both finFET and SGrFET such as power dissipation, noise margin and switching speed to compare the devices under the investigation performance against each other. It is shown that using multi-geometrical feature in SGrFET together with its multi-gate operation can greatly decrease the number of device needed for the logic function without speed degradation and it can be used as a potential candidate in mix-circuit configuration as a multi-gate device. The initial fabrication steps of the novel device explained together with some in-house fabrication process using E-Beam lithography. The fabricated SGrFET is characterised via electrical measurements and used in a circuit configuration

    Development of a fully-depleted thin-body FinFET process

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    The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

    Modeling and Simulation of Negative Capacitance MOSFETs

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    The current and voltage characteristics of a MOSFET device are maily characterized by the source to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern the number of carriers that are able to cross the barrier indicates that to increase the current by a decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades. This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in modern IC based chips with billions of transistors. Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used to achieve a smaller subthreshold swing which would further reduce the power consumption of the devices. In this thesis we have undertaken a simulation based study of such devices to study how the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics. Initially we have taken a compact modeling based approach to study device characteristics in latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like negative output resistance and drain induced barrier rising are observed. Using the compact models developed above, we have analyzed some simple circuits with NC devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices is lesser than that of regular devices due to enhanced gate capacitance and slower response of ferroelectrics. Scaling analysis has been performed to see the performance of NC devices in future technologies. For this we used TCAD analysis coupled with Landau Khalatnikov equation. This analysis shows that NC devices are more e�ective in suppressing short channel e�ects like DIBL and can hence be used for further downscaling of the devices. Finally we develop models to take into account the multidomain Landau equations for ferroelec- tric into account. We have performed such an analysis for a ferroelectric resistor series network. A similar analysis is performed for short channel double gate MOSFET without inter layer metal be- tween ferroelectric and the internal MOS device. This analysis showed that coupling factor between ferroelectric domains plays an important role in the device characteristics

    Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

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    A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

    Silicon- and Graphene-based FETs for THz technology

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    [EN] This Thesis focuses on the study of the response to Terahertz (THz) electromagnetic radiation of different silicon substrate-compatible FETs. Strained-Si MODFETs, state-of- the-art FinFETs and graphene-FETs were studied. The first part of this thesis is devoted to present the results of an experimental and theoretical study of strained-Si MODFETs. These transistors are built by epitaxy of relaxed-SiGe on a conventional Si wafer to permit the fabrication of a strained-Si electron channel to obtain a high-mobility electron gas. Room temperature detection under excitation of 0.15 and 0.3 THz as well as sensitivity to the polarization of incoming radiations were demonstrated. A two-dimensional hydrodynamic-model was developed to conduct TCAD simulations to understand and predict the response of the transistors. Both experimental data and TCAD results were in good agreement demonstrating both the potential of TCAD as a tool for the design of future new THz devices and the excellent performance of strained-Si MODFETs as THz detectors (75 V/W and 0.06 nW/Hz0.5). The second part of the Thesis reports on an experimental study on the THz behavior of modern silicon FinFETs at room temperature. Silicon FinFETs were characterized in the frequency range 0.14-0.44 THz. The results obtained in this study show the potential of these devices as THz detectors in terms of their excellent Responsivity and NEP figures (0.66 kV/W and 0.05 nW/Hz0.5). Finally, a large part of the Thesis is devoted to the fabrication and characterization of Graphene-based FETs. A novel transfer technique and an in-house-developed setup were implemented in the Nanotechnology Clean Room of the USAL and described in detail in this Thesis. The newly developed transfer technique enables to encapsulate a graphene layer between two flakes of h-BN. Raman measurements confirmed the quality of the fabricated graphene heterostructures and, thus, the excellent properties of encapsulated graphene. The asymmetric dual grating gate graphene FET (ADGG-GFET) concept was introduced as an efficient way to improve the graphene response to THz radiation. High quality ADGG-GFETs were fabricated and characterized under THz radiation. DC measurements confirmed the high quality of graphene heterostructures as it was shown on Raman measurements. A clear THz detection was found for both 0.15 THz and 0.3 THz at 4K when the device was voltage biased either using the back or the top gate of the G-FET. Room temperature THz detection was demonstrated at 0.3 THz using the ADGG-GFET. The device shows a Responsivity and NEP around 2.2 mA/W and 0.04 nW/Hz0.5 respectively at respectively at 4K. It was demonstrated the practical use of the studied devices for inspection of hidden objects by using the in-house developed THz imaging system
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