Optimal Content Downloading in Vehicular Networks

We consider a system where users aboard communication-enabled vehicles are interested in downloading different contents from Internet-based servers. This scenario captures many of the infotainment services that vehicular communication is envisioned to enable, including news reporting, navigation maps and software updating, or multimedia file downloading. In this paper, we outline the performance limits of such a vehicular content downloading system by modelling the downloading process as an optimization problem, and maximizing the overall system throughput. Our approach allows us to investigate the impact of different factors, such as the roadside infrastructure deployment, the vehicle-to-vehicle relaying, and the penetration rate of the communication technology, even in presence of large instances of the problem. Results highlight the existence of two operational regimes at different penetration rates and the importance of an efficient, yet 2-hop constrained, vehicle-to-vehicle relaying

The Effect of the Bulk Sales Article on Existing Commercial Practices

Power control is considered as an important means to combat near-far fading effects and maintain acceptable connections in wireless communications systems. When applying power control in practice, the performance is restricted by a number of fundamental limitations. Here, these are addressed from a control theory perspective. Limited update rate, limited feedback bandwidth, time delays, measurement errors, feedback errors, and filtering effects among other aspects all affect the resulting performance, and are related to radio channnel characteristics. Simulations further illustrate the hampering effects

The "MIND" Scalable PIM Architecture

MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture