236 research outputs found

    Serial-data computation in VLSI

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    Residue number system coded differential space-time-frequency coding.

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    Thesis (Ph.D.)-University of KwaZulu-Natal, Durban, 2007.The rapidly growing need for fast and reliable transmission over a wireless channel motivates the development of communication systems that can support high data rates at low complexity. Achieving reliable communication over a wireless channel is a challenging task largely due to the possibility of multipaths which may lead to intersymbol interference (ISI). Diversity techniques such as time, frequency and space are commonly used to combat multipath fading. Classical diversity techniques use repetition codes such that the information is replicated and transmitted over several channels that are sufficiently spaced. In fading channels, the performance across some diversity branches may be excessively attenuated, making throughput unacceptably small. In principle, more powerful coding techniques can be used to maximize the diversity order. This leads to bandwidth expansion or increased transmission power to accommodate the redundant bits. Hence there is need for coding and modulation schemes that provide low error rate performance in a bandwidth efficient manner. If diversity schemes are combined, more independent dimensions become available for information transfer. The first part of the thesis addresses achieving temporal diversity through employing error correcting coding schemes combined with interleaving. Noncoherent differential modulation does not require explicit knowledge or estimate of the channel, instead the information is encoded in the transitions. This lends itself to the possibility of turbo-like serial concatenation of a standard outer channel encoder with an inner modulation code amenable to noncoherent detection through an interleaver. An iterative approach to joint decoding and demodulation can be realized by exchanging soft information between the decoder and the demodulator. This has been shown to be effective and hold hope for approaching capacity over fast fading channels. However most of these schemes employ low rate convolutional codes as their channel encoders. In this thesis we propose the use of redundant residue number system codes. It is shown that these codes can achieve comparable performance at minimal complexity and high data rates. The second part deals with the possibility of combining several diversity dimensions into a reliable bandwidth efficient communication scheme. Orthogonal frequency division multiplexing (OFDM) has been used to combat multipaths. Combining OFDM with multiple-input multiple-output (MIMO) systems to form MIMO-OFDM not only reduces the complexity by eliminating the need for equalization but also provides large channel capacity and a high diversity potential. Space-time coded OFDM was proposed and shown to be an effective transmission technique for MIMO systems. Spacefrequency coding and space-time-frequency coding were developed out of the need to exploit the frequency diversity due to multipaths. Most of the proposed schemes in the literature maximize frequency diversity predominantly from the frequency-selective nature of the fading channel. In this thesis we propose the use of residue number system as the frequency encoder. It is shown that the proposed space-time-frequency coding scheme can maximize the diversity gains over space, time and frequency domains. The gain of MIMO-OFDM comes at the expense of increased receiver complexity. Furthermore, most of the proposed space-time-frequency coding schemes assume frequency selective block fading channels which is not an ideal assumption for broadband wireless communications. Relatively high mobility in broadband wireless communications systems may result in high Doppler frequency, hence time-selective (rapid) fading. Rapidly changing channel characteristics impedes the channel estimation process and may result in incorrect estimates of the channel coefficients. The last part of the thesis deals with the performance of differential space-time-frequency coding in fast fading channels

    A computer-aided design for digital filter implementation

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    Imperial Users onl

    Combined Industry, Space and Earth Science Data Compression Workshop

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    The sixth annual Space and Earth Science Data Compression Workshop and the third annual Data Compression Industry Workshop were held as a single combined workshop. The workshop was held April 4, 1996 in Snowbird, Utah in conjunction with the 1996 IEEE Data Compression Conference, which was held at the same location March 31 - April 3, 1996. The Space and Earth Science Data Compression sessions seek to explore opportunities for data compression to enhance the collection, analysis, and retrieval of space and earth science data. Of particular interest is data compression research that is integrated into, or has the potential to be integrated into, a particular space or earth science data information system. Preference is given to data compression research that takes into account the scien- tist's data requirements, and the constraints imposed by the data collection, transmission, distribution and archival systems

    Adaptive Precision Floating-Point Arithmetic and Fast Robust Geometric Predicates

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    Exact computer arithmetic has a variety of uses including, but not limited to, the robust implementation of geometric algorithms. This report has three purposes. The first is to offer fast software-level algorithms for exact addition and multiplication of arbitrary precision floating-point values. The second is to propose a technique for adaptive-precision arithmetic that can often speed these algorithms when one wishes to perform multiprecision calculations that do not always require exact arithmetic, but must satisfy some error bound. The third is to provide a practical demonstration of these techniques, in the form of implementations of several common geometric calculations whose required degree of accuracy depends on their inputs. These robust geometric predicates are adaptive; their running time depends on the degree of uncertainty of the result, and is usually small. These algorithms work on computers whose floating-point arithmetic uses radix two and exact rounding, including machines complying with the IEEE 754 standard. The inputs to the predicates may be arbitrary single or double precision floating-point numbers. C code is publicly available for the 2D and 3D orientation and incircle tests, an

    Algorithms and VLSI architectures for parametric additive synthesis

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    A parametric additive synthesis approach to sound synthesis is advantageous as it can model sounds in a large scale manner, unlike the classical sinusoidal additive based synthesis paradigms. It is known that a large body of naturally occurring sounds are resonant in character and thus fit the concept well. This thesis is concerned with the computational optimisation of a super class of form ant synthesis which extends the sinusoidal parameters with a spread parameter known as band width. Here a modified formant algorithm is introduced which can be traced back to work done at IRCAM, Paris. When impulse driven, a filter based approach to modelling a formant limits the computational work-load. It is assumed that the filter's coefficients are fixed at initialisation, thus avoiding interpolation which can cause the filter to become chaotic. A filter which is more complex than a second order section is required. Temporal resolution of an impulse generator is achieved by using a two stage polyphase decimator which drives many filterbanks. Each filterbank describes one formant and is composed of sub-elements which allow variation of the formant’s parameters. A resource manager is discussed to overcome the possibility of all sub- banks operating in unison. All filterbanks for one voice are connected in series to the impulse generator and their outputs are summed and scaled accordingly. An explorative study of number systems for DSP algorithms and their architectures is investigated. I invented a new theoretical mechanism for multi-level logic based DSP. Its aims are to reduce the number of transistors and to increase their functionality. A review of synthesis algorithms and VLSI architectures are discussed in a case study between a filter based bit-serial and a CORDIC based sinusoidal generator. They are both of similar size, but the latter is always guaranteed to be stable

    New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

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    Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm\u27s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its performance in parallel execution on a processor of interconnected functional units employing fast, low-precision fixed-point arithmetic. It is shown that the frequent occurrence of saturation when 8-bit signed arithmetic is used severely degrades the performance of the algorithm compared with decoding using higher-precision arithmetic. A technique of limiting the magnitude of certain intermediate variables of the algorithm, the extrinsic values, is proposed and shown to eliminate most occurrences of saturation, resulting in performance with 8-bit decoding nearly equal to that achieved with higher-precision decoding. We show that the interconnection latency can have a significant detrimental effect of the throughput of the turbo-decoding message-passing algorithm, which is illustrated for a type of high-performance digital signal processor known as a stream processor. Two alternatives to the standard schedule of message-passing and parity-check operations are proposed for the algorithm. Both alternatives markedly reduce the interconnection latency, and both result in substantially greater throughput than the standard schedule with no increase in the probability of error

    Proceedings of the 7th Conference on Real Numbers and Computers (RNC'7)

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    These are the proceedings of RNC7

    Techniques for the realization of ultra- reliable spaceborne computer Final report

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    Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer

    Conference on the Programming Environment for Development of Numerical Software

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    Systematic approaches to numerical software development and testing are presented
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