A Purely Symbol-Based Precoded and LDPC-Coded Iterative-Detection Assisted Sphere-Packing Modulated Space-Time Coding Scheme

In this contribution, we propose a purely symbol-based LDPC-coded scheme based on a Space-Time Block Coding (STBC) signal construction method that combines orthogonal design with sphere packing, referred to here as (STBCSP). We demonstrate that useful performance improvements may be attained when sphere packing aided modulation is concatenated with non-binary LDPC especially, when performing purely symbol-based turbo detection by exchanging extrinsic information between the non-binary LDPC decoder and a rate-1 non-binary inner precoder. We also investigate the convergence behaviour of this symbol-based concatenated scheme with the aid of novel non-binary Extrinsic Information Transfer (EXIT) Charts. The proposed symbol-based turbo-detected STBC-SP scheme exhibits a 'turbo-cliff' at Eb/N0 = 5.0 dB and achieves an Eb/N0 gain of 19.2dB at a BER of 10-5 over Alamouti’s scheme

CROSSTALK-RESILIANT CODING FOR HIGH DENSITY DIGITAL RECORDING

Increasing the track density in magnetic systems is very difficult due to inter-track interference (ITI) caused by the magnetic field of adjacent tracks. This work presents a two-track partial response class 4 magnetic channel with linear and symmetrical ITI; and explores modulation codes, signal processing methods and error correction codes in order to mitigate the effects of ITI. Recording codes were investigated, and a new class of two-dimensional run-length limited recording codes is described. The new class of codes controls the type of ITI and has been found to be about 10% more resilient to ITI compared to conventional run-length limited codes. A new adaptive trellis has also been described that adaptively solves for the effect of ITI. This has been found to give gains up to 5dB in signal to noise ratio (SNR) at 40% ITI. It was also found that the new class of codes were about 10% more resilient to ITI compared to conventional recording codes when decoded with the new trellis. Error correction coding methods were applied, and the use of Low Density Parity Check (LDPC) codes was investigated. It was found that at high SNR, conventional codes could perform as well as the new modulation codes in a combined modulation and error correction coding scheme. Results suggest that high rate LDPC codes can mitigate the effect of ITI, however the decoders have convergence problems beyond 30% ITI

EQUALISATION TECHNIQUES FOR MULTI-LEVEL DIGITAL MAGNETIC RECORDING

A large amount of research has been put into areas of signal processing, medium design, head and servo-mechanism design and coding for conventional longitudinal as well as perpendicular magnetic recording. This work presents some further investigation in the signal processing and coding aspects of longitudinal and perpendicular digital magnetic recording. The work presented in this thesis is based upon numerical analysis using various simulation methods. The environment used for implementation of simulation models is C/C + + programming. Important results based upon bit error rate calculations have been documented in this thesis. This work presents the new designed Asymmetric Decoder (AD) which is modified to take into account the jitter noise and shows that it has better performance than classical BCJR decoders with the use of Error Correction Codes (ECC). In this work, a new method of designing Generalised Partial Response (GPR) target and its equaliser has been discussed and implemented which is based on maximising the ratio of the minimum squared euclidean distance of the PR target to the noise penalty introduced by the Partial Response (PR) filter. The results show that the new designed GPR targets have consistently better performance in comparison to various GPR targets previously published. Two methods of equalisation including the industry's standard PR, and a novel Soft-Feedback- Equalisation (SFE) have been discussed which are complimentary to each other. The work on SFE, which is a novelty of this work, was derived from the problem of Inter Symbol Interference (ISI) and noise colouration in PR equalisation. This work also shows that multi-level SFE with MAP/BCJR feedback based magnetic recording with ECC has similar performance when compared to high density binary PR based magnetic recording with ECC, thus documenting the benefits of multi-level magnetic recording. It has been shown that 4-level PR based magnetic recording with ECC at half the density of binary PR based magnetic recording has similar performance and higher packing density by a factor of 2. A novel technique of combining SFE and PR equalisation to achieve best ISI cancellation in a iterative fashion has been discussed. A consistent gain of 0.5 dB and more is achieved when this technique is investigated with application of Maximum Transition Run (MTR) codes. As the length of the PR target in PR equalisation increases, the gain achieved using this novel technique consistently increases and reaches up to 1.2 dB in case of EEPR4 target for a bit error rate of 10-5

Near-capacity fixed-rate and rateless channel code constructions

Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. Moreover, new applications such as eHealth, autonomous vehicles, and connected ambulances set new demands on the reliability, latency, and data-rate of wireless communication systems, pushing forward technology developments. Massive multiple-input multiple-output (MIMO) is a technology, which is employed in the 5G standard, offering the benefits to fulfill these requirements. In massive MIMO systems, base station (BS) is equipped with a very large number of antennas, serving several users equipments (UEs) simultaneously in the same time and frequency resource. The high spatial multiplexing in massive MIMO systems, improves the data rate, energy and spectral efficiencies as well as the link reliability of wireless communication systems. The link reliability can be further improved by employing channel coding technique. Spatially coupled serially concatenated codes (SC-SCCs) are promising channel coding schemes, which can meet the high-reliability demands of wireless communication systems beyond 5G (B5G). Given the close-to-capacity error correction performance and the potential to implement a high-throughput decoder, this class of code can be a good candidate for wireless systems B5G. In order to achieve the above-mentioned advantages, sophisticated algorithms are required, which impose challenges on the baseband signal processing. In case of massive MIMO systems, the processing is much more computationally intensive and the size of required memory to store channel data is increased significantly compared to conventional MIMO systems, which are due to the large size of the channel state information (CSI) matrix. In addition to the high computational complexity, meeting latency requirements is also crucial. Similarly, the decoding-performance gain of SC-SCCs also do come at the expense of increased implementation complexity. Moreover, selecting the proper choice of design parameters, decoding algorithm, and architecture will be challenging, since spatial coupling provides new degrees of freedom in code design, and therefore the design space becomes huge. The focus of this thesis is to perform co-optimization in different design levels to address the aforementioned challenges/requirements. To this end, we employ system-level characteristics to develop efficient algorithms and architectures for the following functional blocks of digital baseband processing. First, we present a fast Fourier transform (FFT), an inverse FFT (IFFT), and corresponding reordering scheme, which can significantly reduce the latency of orthogonal frequency-division multiplexing (OFDM) demodulation and modulation as well as the size of reordering memory. The corresponding VLSI architectures along with the application specific integrated circuit (ASIC) implementation results in a 28 nm CMOS technology are introduced. In case of a 2048-point FFT/IFFT, the proposed design leads to 42% reduction in the latency and size of reordering memory. Second, we propose a low-complexity massive MIMO detection scheme. The key idea is to exploit channel sparsity to reduce the size of CSI matrix and eventually perform linear detection followed by a non-linear post-processing in angular domain using the compressed CSI matrix. The VLSI architecture for a massive MIMO with 128 BS antennas and 16 UEs along with the synthesis results in a 28 nm technology are presented. As a result, the proposed scheme reduces the complexity and required memory by 35%–73% compared to traditional detectors while it has better detection performance. Finally, we perform a comprehensive design space exploration for the SC-SCCs to investigate the effect of different design parameters on decoding performance, latency, complexity, and hardware cost. Then, we develop different decoding algorithms for the SC-SCCs and discuss the associated decoding performance and complexity. Also, several high-level VLSI architectures along with the corresponding synthesis results in a 12 nm process are presented, and various design tradeoffs are provided for these decoding schemes

Near Shannon limit precoded concatenated zigzag codes

Concatenated zigzag (CZ) codes are a class of multidimensional parallel concatenated codes, which have some favorable properties, such as low encoding and decoding complexities and rate compatibility. However, there is a noticeable gap between the performance of a standard CZ code and the corresponding Shannon limit. To overcome this problem, we apply the precoding technique recently developed by Abbasfar et al. to CZ codes, resulting in a novel class of turbo-like codes, termed precoded CZ codes. The EXIT chart tool is used for convergence analysis and performance optimization. We show that the proposed precoded CZ codes have thresholds within 0.25 dB of the Shannon limit for a wide code rate range of [0.5, 20/21]. Extensive simulation results are provided to demonstrate that optimized precoded CZ codes exhibit good performance at different code rates and different block lengths