Contributions to adaptive equalization and timing recovery for optical storage systems

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Near minimum bit-error rate equalizer adaptation for PRML systems

Receivers for partial response maximum-likelihood systems typically use a linear equalizer followed by a Viterbi detector. The equalizer tries to confine the channel intersymbol interference to a short span in order to limit the implementation complexity of the Viterbi detector. Equalization is usually made adaptive in order to compensate for channel variations. Conventional adaptation techniques, e.g. LMS, are in general suboptimal in terms of bit-error rate. In this paper we present a new equalizer adaptation algorithm that seeks to minimize bit-error rate at the Viterbi detector output. The algorithm extracts information from the sequenced amplitude margin (SAM) histogram and incorporates a selection mechanism that focuses adaptation on particular data and noise realizations. From a complexity standpoint, the algorithm is as simple as the conventional LMS algorithm. Simulation results, for an idealized optical storage channel, confirm a substantial performance improvement relative to existing adaptation algorithm

Design of adaptive analog filters for magnetic front-end read channels

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company

Design and Implementation of Belief Propagation Symbol Detectors for Wireless Intersymbol Interference Channels

In modern wireless communication systems, intersymbol interference (ISI) introduced by frequency selective fading is one of the major impairments to reliable data communication. In ISI channels, the receiver observes the superposition of multiple delayed reflections of the transmitted signal, which will result errors in the decision device. As the data rate increases, the effect of ISI becomes severe. To combat ISI, equalization is usually required for symbol detectors. The optimal maximum-likelihood sequence estimation (MLSE) based on the Viterbi algorithm (VA) may be used to estimate the transmitted sequence in the presence of the ISI. However, the computational complexity of the MLSE increases exponentially with the length of the channel impulse response (CIR). Even in channels which do not exhibit significant time dispersion, the length of the CIR will effectively increase as the sampling rate goes higher. Thus the optimal MLSE is impractical to implement in the majority of practical wireless applications. This dissertation is devoted to exploring practically implementable symbol detectors with near-optimal performance in wireless ISI channels. Particularly, we focus on the design and implementation of an iterative detector based on the belief propagation (BP) algorithm. The advantage of the BP detector is that its complexity is solely dependent on the number of nonzero coefficients in the CIR, instead of the length of the CIR. We also extend the work of BP detector design for various wireless applications. Firstly, we present a partial response BP (PRBP) symbol detector with near-optimal performance for channels which have long spanning durations but sparse multipath structure. We implement the architecture by cascading an adaptive linear equalizer (LE) with a BP detector. The channel is first partially equalized by the LE to a target impulse response (TIR) with only a few nonzero coefficients remaining. The residual ISI is then canceled by a more sophisticated BP detector. With the cascaded LE-BP structure, the symbol detector is capable to achieve a near-optimal error rate performance with acceptable implementation complexity. Moreover, we present a pipeline high-throughput implementation of the detector for channel length 30 with quadrature phase-shift keying (QPSK) modulation. The detector can achieve a maximum throughput of 206 Mb/s with an estimated core area of 3.162 mm^{2} using 90-nm technology node. At a target frequency of 515 MHz, the dynamic power is about 1.096 W. Secondly, we investigate the performance of aforementioned PRBP detector under a more generic 3G channel rather than the sparse channel. Another suboptimal partial response maximum-likelihood (PRML) detector is considered for comparison. Similar to the PRBP detector, the PRML detector also employs a hybrid two-stage scheme, in order to allow a tradeoff between performance and complexity. In simulations, we consider a slow fading environment and use the ITU-R 3G channel models. From the numerical results, it is shown that in frequency-selective fading wireless channels, the PRBP detector provides superior performance over both the traditional minimum mean squared error linear equalizer (MMSE-LE) and the PRML detector. Due to the effect of colored noise, the PRML detector in fading wireless channels is not as effective as it is in magnetic recording applications. Thirdly, we extend our work to accommodate the application of Advanced Television Systems Committee (ATSC) digital television (DTV) systems. In order to reduce error propagation caused by the traditional decision feedback equalizer (DFE) in DTV receiver, we present an adaptive decision feedback sparsening filter BP (DFSF-BP) detector, which is another form of PRBP detector. Different from the aforementioned LE-BP structure, in the DFSF-BP scheme, the BP detector is followed by a nonlinear filter called DFSF as the partial response equalizer. In the first stage, the DFSF employs a modified feedback filter which leaves the strongest post-cursor ISI taps uncorrected. As a result, a long ISI channel is equalized to a sparse channel having only a small number of nonzero taps. In the second stage, the BP detector is applied to mitigate the residual ISI. Since the channel is typically time-varying and suffers from Doppler fading, the DFSF is adapted using the least mean square (LMS) algorithm, such that the amplitude and the locations of the nonzero taps of the equalized sparse channel appear to be fixed. As such, the channel appears to be static during the second stage of equalization which consists of the BP detector. Simulation results demonstrate that the proposed scheme outperforms the traditional DFE in symbol error rate, under both static channels and dynamic ATSC channels. Finally, we study the symbol detector design for cooperative communications, which have attracted a lot of attention recently for its ability to exploit increased spatial diversity available at distributed antennas on other nodes. A system framework employing non-orthogonal amplify-and-forward half-duplex relays through ISI channels is developed. Based on the system model, we first design and implement an optimal maximum-likelihood detector based on the Viterbi algorithm. As the relay period increases, the effective CIR between the source and the destination becomes long and sparse, which makes the optimal detector impractical to implement. In order to achieve a balance between the computational complexity and performance, several sub-optimal detectors are proposed. We first present a multitrellis Viterbi algorithm (MVA) based detector which decomposes the original trellis into multiple parallel irregular sub-trellises by investigating the dependencies between the received symbols. Although MVA provides near-optimal performance, it is not straightforward to decompose the trellis for arbitrary ISI channels. Next, the decision feedback sequence estimation (DFSE) based detector and BP-based detector are proposed for cooperative ISI channels. Traditionally these two detectors are used with fixed, static channels. In our model, however, the effective channel is periodically time-varying, even when the component channels themselves are static. Consequently, we modify these two detector to account for cooperative ISI channels. Through simulations in frequency selective fading channels, we demonstrate the uncoded performance of the DFSE detector and the BP detector when compared to the optimal MLSE detector. In addition to quantifying the performance of these detectors, we also include an analysis of the implementation complexity as well as a discussion on complexity/performance tradeoffs

Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization

This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm

Graph-Based Decoding in the Presence of ISI

We propose an approximation of maximum-likelihood detection in ISI channels based on linear programming or message passing. We convert the detection problem into a binary decoding problem, which can be easily combined with LDPC decoding. We show that, for a certain class of channels and in the absence of coding, the proposed technique provides the exact ML solution without an exponential complexity in the size of channel memory, while for some other channels, this method has a non-diminishing probability of failure as SNR increases. Some analysis is provided for the error events of the proposed technique under linear programming.Comment: 25 pages, 8 figures, Submitted to IEEE Transactions on Information Theor

CROSSTALK-RESILIANT CODING FOR HIGH DENSITY DIGITAL RECORDING

Increasing the track density in magnetic systems is very difficult due to inter-track interference (ITI) caused by the magnetic field of adjacent tracks. This work presents a two-track partial response class 4 magnetic channel with linear and symmetrical ITI; and explores modulation codes, signal processing methods and error correction codes in order to mitigate the effects of ITI. Recording codes were investigated, and a new class of two-dimensional run-length limited recording codes is described. The new class of codes controls the type of ITI and has been found to be about 10% more resilient to ITI compared to conventional run-length limited codes. A new adaptive trellis has also been described that adaptively solves for the effect of ITI. This has been found to give gains up to 5dB in signal to noise ratio (SNR) at 40% ITI. It was also found that the new class of codes were about 10% more resilient to ITI compared to conventional recording codes when decoded with the new trellis. Error correction coding methods were applied, and the use of Low Density Parity Check (LDPC) codes was investigated. It was found that at high SNR, conventional codes could perform as well as the new modulation codes in a combined modulation and error correction coding scheme. Results suggest that high rate LDPC codes can mitigate the effect of ITI, however the decoders have convergence problems beyond 30% ITI

Enhanced coding, clock recovery and detection for a magnetic credit card

Merged with duplicate record 10026.1/2299 on 03.04.2017 by CS (TIS)This thesis describes the background, investigation and construction of a system for storing data on the magnetic stripe of a standard three-inch plastic credit in: inch card. Investigation shows that the information storage limit within a 3.375 in by 0.11 in rectangle of the stripe is bounded to about 20 kBytes. Practical issues limit the data storage to around 300 Bytes with a low raw error rate: a four-fold density increase over the standard. Removal of the timing jitter (that is prob-' ably caused by the magnetic medium particle size) would increase the limit to 1500 Bytes with no other system changes. This is enough capacity for either a small digital passport photograph or a digitized signature: making it possible to remove printed versions from the surface of the card. To achieve even these modest gains has required the development of a new variable rate code that is more resilient to timing errors than other codes in its efficiency class. The tabulation of the effects of timing errors required the construction of a new code metric and self-recovering decoders. In addition, a new method of timing recovery, based on the signal 'snatches' has been invented to increase the rapidity with which a Bayesian decoder can track the changing velocity of a hand-swiped card. The timing recovery and Bayesian detector have been integrated into one computation (software) unit that is self-contained and can decode a general class of (d, k) constrained codes. Additionally, the unit has a signal truncation mechanism to alleviate some of the effects of non-linear distortion that are present when a magnetic card is read with a magneto-resistive magnetic sensor that has been driven beyond its bias magnetization. While the storage density is low and the total storage capacity is meagre in comparison with contemporary storage devices, the high density card may still have a niche role to play in society. Nevertheless, in the face of the Smart card its long term outlook is uncertain. However, several areas of coding and detection under short-duration extreme conditions have brought new decoding methods to light. The scope of these methods is not limited just to the credit card