Single flux quantum circuits with damping based on dissipative transmission lines

We propose and demonstrate the functioning of a special Rapid Single Flux Quantum (RSFQ) circuit with frequency-dependent damping. This damping is achieved by shunting individual Josephson junctions by pieces of open-ended RC transmission lines. Our circuit includes a toggle flip-flop cell, Josephson transmission lines transferring single flux quantum pulses to and from this cell, as well as DC/SFQ and SFQ/DC converters. Due to the desired frequency-dispersion in the RC line shunts which ensures sufficiently low noise at low frequencies, such circuits are well-suited for integrating with the flux/phase Josephson qubit and enable its efficient control.Comment: 6 pages incl. 6 figure

High Density Fabrication Process for Single Flux Quantum Circuits

We implemented, optimized and fully tested over multiple runs a superconducting Josephson junction fabrication process tailored for the integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient single flux quantum (ERSFQ) circuits with the critical currents reduced by factor of ~10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 uA unit critical current fabricated with a 10 uA/um2 critical current density. In order to circumvent the substantial size increase of the SFQ circuit inductors, we employed a NbN high kinetic inductance layer (HKIL) with a 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with a 4.0 ohm/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 um height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive Process Control Monitor chip set.Comment: 10 pages, 5 figures, 1 tabl

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors.Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 201

Beyond Moore's technologies: operation principles of a superconductor alternative

The predictions of Moore's law are considered by experts to be valid until 2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore's alternative for the development of supercomputers. In this paper, we consider operation principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined.Comment: OPEN ACCES