Assessing Random Dynamical Network Architectures for Nanoelectronics

Independent of the technology, it is generally expected that future nanoscale devices will be built from vast numbers of densely arranged devices that exhibit high failure rates. Other than that, there is little consensus on what type of technology and computing architecture holds most promises to go far beyond today's top-down engineered silicon devices. Cellular automata (CA) have been proposed in the past as a possible class of architectures to the von Neumann computing architecture, which is not generally well suited for future parallel and fine-grained nanoscale electronics. While the top-down engineered semi-conducting technology favors regular and locally interconnected structures, future bottom-up self-assembled devices tend to have irregular structures because of the current lack precise control over these processes. In this paper, we will assess random dynamical networks, namely Random Boolean Networks (RBNs) and Random Threshold Networks (RTNs), as alternative computing architectures and models for future information processing devices. We will illustrate that--from a theoretical perspective--they offer superior properties over classical CA-based architectures, such as inherent robustness as the system scales up, more efficient information processing capabilities, and manufacturing benefits for bottom-up designed devices, which motivates this investigation. We will present recent results on the dynamic behavior and robustness of such random dynamical networks while also including manufacturing issues in the assessment.Comment: 8 pages, 6 figures, IEEE/ACM Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, Jun 12-13, 200

Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with 10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.Comment: 13 pages, 5 figure, journal publicatio

Adaptive code division multiple access protocol for wireless network-on-chip architectures

Massive levels of integration following Moore\u27s Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects

CMOS Integration of High Performance Quantum Dot Lasers For Silicon Photonics

Integration of III-V components on Si substrates is required for realizing the promise of Silicon Photonic systems. Specifically, the direct bandgap of many III-V materials is required for light sources, efficient modulators and photodetectors. Several different approaches have been taken to integrate III-V lasers into the silicon photonic platform, such as wafer bonding, direct growth, butt coupling, etc. Here, we have devised a novel laser design that overcomes the above limitations. In our approach, we use InAs quantum dot (QD) lasers monolithically integrated with silicon waveguides and other Si photonic passive components. Due to their unique structures, the QD lasers have been proven by several groups to have the combination of high temperature stability, large modulation bandwidth and low power consumption compared with their quantum well counterparts, which makes it an ideal candidate for Si photonic applications. The first section of this dissertation introduces the theory and novelty of QD lasers, the DC and RF characterization methods of QD lasers are also discussed. The second section is focused on the growth of QD gain chip which a broadband gain chip based on QD inhomogeneous broadening properties was demonstrated. In third section, the lasers devices are built on Si substrate by Pd wafer bonding technology. Firstly, a ridge waveguide QD laser is demonstrated in this section which have better heat dissipation and lower threshold current compared to the unbonded lasers. In section four, a on Si comb laser is also developed. Due to inhomogeneous broadening and ultrafast carrier dynamics, InAs quantum dots have key advantages that make them well suited for Mode-locked lasers (MLLs). In section five, a passively mode-locked InAs quantum dots laser on Si is achieved at a repetition rate of ~7.3 GHz under appropriate bias conditions. In section six, a butt-joint integration configuration based on QD lasers and silicon photonics ring resonator is tested by using to translation stage. In order to achieve the on chip butt-joint integration, an on chip laser facet was created in section seven. A novel facet etching method is developed by using Br-ion beam assist etching (Br-IBAE). In section eight, a Pd-GaAs butt-joint integration platform was proposed, a hybrid tunable QD laser which consist of a QD SOA gain chip butt joint coupled with a passive Si3N4 photonic integrated circuit is proof of concept by using an external booster SOA coupled with a Si3N4 ring reflector feedback circuit. The final section summarized the work discussed in this thesis and also discussed some future approaches by using QD lasers integrated with silicon photonics integrated circuits based on the Pd-GaAs wafer bonding butt-joint coupled platform

Doctor of Philosophy

dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy