Methodology for standard cell compliance and detailed placement for triple patterning lithography

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Layout decomposition for triple patterning lithography

Nowadays the semiconductor industry is continuing to advance the limits of physics as the feature size of the chip keeps shrinking. Products of the 22 nm technology node are already available on the market, and there are many ongoing research studies for the 14/10 nm technology nodes and beyond. Due to the physical limitations, the traditional 193 nm immersion lithography is facing huge challenges in fabricating such tiny features. Several types of next-generation lithography techniques have been discussed for years, such as {\em extreme ultra-violet} (EUV) lithography, {\em E-beam direct write}, and {\em block copolymer directed self-assembly} (DSA). However, the source power for EUV is still an unresolved issue. The low throughput of E-beam makes it impractical for massive productions. DSA is still under calibration in research labs and is not ready for massive industrial deployment. Traditionally features are fabricated under single litho exposure. As feature size becomes smaller and smaller, single exposure is no longer adequate in satisfying the quality requirements. {\em Double patterning lithography} (DPL) utilizes two litho exposures to manufacture features on the same layer. Features are assigned to two masks, with each mask going through a separate litho exposure. With one more mask, the effective pitch is doubled, thus greatly enhancing the printing resolution. Therefore, DPL has been widely recognized as a feasible lithography solution in the sub-22 nm technology node. However, as the technology continues to scale down to 14/10 nm and beyond, DPL begins to show its limitations as it introduces a high number of stitches, which increases the manufacturing cost and potentially leads to functional errors of the circuits. {\em Triple pattering lithography} (TPL) uses three masks to print the features on the same layer, which further enhances the printing resolution. It is a natural extension for DPL with three masks available, and it is one of the most promising solutions for the 14/10 nm technology node and beyond. In this thesis, TPL decomposition for standard-cell-based designs is extensively studied. We proposed a polynomial time triple patterning decomposition algorithm which guarantees finding a TPL decomposition if one exists. For complex designs with stitch candidates, our algorithm is able to find a solution with the optimal number of stitches. For standard-cell-based designs, there are additional coloring constraints where the same type of cell should be fabricated following the same pattern. We proposed an algorithm that is guaranteed to find a solution when one exists. The framework of the algorithm is also extended to pattern-based TPL decompositions, where the cost of a decomposition can be minimized given a library of different patterns. The polynomial time TPL algorithm is further optimized in terms of runtime and memory while keeping the solution quality unaffected. We also studied the TPL aware detailed placement problem, where our approach is guaranteed to find a legal detailed placement satisfying TPL coloring constraints as well as minimizing the {\em half-perimeter wire length} (HPWL). Finally, we studied the problem of performance variations due to mask misalignment in {\em multiple patterning decompositions} (MPL). For advanced technology nodes, process variations (mainly mask misalignment) have significant influences on the quality of fabricated circuits, and often lead to unexpected power/timing degenerations. Mask misalignment would complicate the way of simulating timing closure if engineers do not understand the underlying effects of mask misalignment, which only exists in multiple patterning decompositions. We mathematically proved the worst-case scenarios of coupling capacitance incurred by mask misalignment in MPL decompositions. A graph model is proposed which is guaranteed to compute the tight upper bound on the worst-case coupling capacitance of any MPL decompositions for a given layout

Design Rules in VLSI Routing

One of the last major steps in the design of highly integrated circuits (VLSI design) is routing. The task of routing is to compute disjoint sets of wires connecting different parts of a chip in order to realize the desired electrical connectivity. Design rules define restrictions on the minimum distance and geometry of metal shapes. The intent of most design rules is to forbid patterns that cannot be manufactured well in the lithographic production process. This process has become extremely difficult with the current small feature sizes of 32 nm and below, which are still being manufactured using 193 nm wavelength technology. Because of this, the design rules of modern technologies have become very complex, and computing a routing with a sufficiently low number of design rule violations is a difficult task for automated routing tools. In this thesis we present in detail how design rules can be handled efficiently. We develop an appropriate design rule model which considerably reduces complexity while not being too restrictive. This involves mapping complex polygon-based rules to simpler rectangle-based rules and building equivalence classes of shapes with respect to their minimum distance requirements. Our model enables efficient checking of minimum distance rules, which has to be done dozens of times in each routing run. We also discuss efficient data structures that are necessary to achieve this. We implemented our design rule model within BonnRoute, the routing tool of the BonnTools, a software package for VLSI physical design developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. The result is a new module of BonnRoute, called BonnRoutRules, which computes this design rule model and embeds BonnRoute in the complex routing environment of current technologies. The BonnRouteRules module was a key part in enabling BonnRoute to route current 32 nm and 22 nm chips. We describe the combined routing flow used by IBM in practice, in which BonnRoute solves the main routing task and an industrial standard router is used for postprocessing. We present detailed experimental results of this flow on real-world designs. The results show that this combined flow produces routings with almost no remaining design rule violations, which proves that our design rule model works well in practice. Furthermore, compared to the industrial standard router alone, the combination with BonnRoute provides several significant benefits: It has 24% less runtime, 5% less wiring length, and over 90% less detours, which shows that with this flow we have an excellent routing tool in practice

Compounding in Namagowab and English: (exploring meaning creation in compounds)

This essay investigates compounding in Namagowab and English, which belong to two widely divergent groups of languages, the Khoesan and Indo-European, respectively. The first motive is to investigate how and why new words are created from existing ones. The reading and data interpretation seeks an understanding of word formation and an overview of semantic compositionality, structure and productivity, within the broad context of cognitive, lexicalist and distributed morphology paradigms. This coupled with history reading about the languages and its people, is used to speculate about why compounds feature in lexical creation. Compounding is prevalent in both languages and their distance in terms of phylogenetic relationships should allow limited generalizing about these processes of formation. Word lists taken from dictionaries in both languages were analyzed by entering the words in Excel spreadsheets so that various attributes of these words, such as word type, compound class (Noun, Verb, Preposition, Adjective and Adverb) and constituent class could be counted, and described with formulae, and compound and constituent meaning analyzed. The conclusion was that socio historical factors such as language contact, and aspects of cognition such as memory and transparency, account for compounding in a language in addition to typology

Device Modelling of Perovskite Solar Cells

This thesis is primarily concerned with the electrical characterization and modelling of perovskite solar cells. Perovskite cells are a new player in the photovoltaic arena with several intriguing properties. One of these is the presence of intrinsic mobile ions which make these semiconductors simultaneously ionic conductors at room temperature. The presence of mobile ions is significant in that it leads to a number of transient behaviours in optoelectronic measurements, including nominally simple current-voltage measurements where the phenomena are broadly labelled as aspects of ``I-V hysteresis''. The first two-thirds of this thesis describes our work on extended drift-diffusion models which incorporate the presence of mobile ions into the conventional equations of semiconductor physics. These allow us to uncover mechanistic explanations for a variety of transient behaviours which are broadly caused by coupling between electronic and ion dynamics. The first third (Chapter 2) deals with hysteresis in the form of rate-dependent I-V sweeps: a selection of unusual measurements of this type is presented including a temporary enhancement in open-circuit voltage following prolonged periods of negative bias, dramatically S-shaped current-voltage sweeps, decreased current extraction following positive biasing or ``inverted hysteresis'', and non-monotonic transient behaviours in the dark and the light. This initial study is supplemented with a more in-depth investigation of inverted hysteresis and its correlation with band-alignment. The second third (Chapter 3) delves deeper into electrical characterization with a first-principles study of electrical impedance spectroscopy. We focus on accounting for features in the measured capacitance spectrum (sufficient for a full account of the total impedance due to the Kramers-Kronig relations) of standard-structure (non-inverted) perovskite cells. Here our models make clear the necessity of distinguishing fundamental contributions to the measured capacitance due to charging, from those due to currents delayed by slow processes such as ion migration. With this distinction clearly established we provide a detailed account of all the major features observed in impedance measurements of these cells, including the exotic and previously puzzling appearance of giant photo-induced capacitance, loop features and negative capacitance. The final part of this thesis in Chapter 4 concerns the integration of perovskite cells into tandem arrangements with a partner such as the crystalline silicon cell. Of relevance to any thin-film solar cell, and to 4-terminal tandem cells in particular, is the specifications of its transparent conductor layers. We analyze transparent conductor requirements under different regimes of metallization (the addition of metallic bus-bars or fingers). Here a key parameter is the minimal achievable wire width, which dictates the necessary tradeoff between transparency and conductivity in the underlying transparent conductor. We identify \SI{30}{\micro \metre} as a critical width below which many emerging transparent conducting layers such as carbon nanotubes and graphene become competitive with state-of-the-art transparent conductive oxides such as ITO for a stand-alone perovskite cell. We also discuss a novel strategy for integrating perovskite and Si cells into a single monolithic structure without the need for a tunnel junction or recombination layer. This is identified as being possible due to the presence of interfacial sub-gap states which can facilitate high-conductivity ohmic contact between TiO$_2$ and p-type Si, and has significant advantages in terms of reducing optical losses and processing steps

Proceedings of the VIIth GSCP International Conference

The 7th International Conference of the Gruppo di Studi sulla Comunicazione Parlata, dedicated to the memory of Claire Blanche-Benveniste, chose as its main theme Speech and Corpora. The wide international origin of the 235 authors from 21 countries and 95 institutions led to papers on many different languages. The 89 papers of this volume reflect the themes of the conference: spoken corpora compilation and annotation, with the technological connected fields; the relation between prosody and pragmatics; speech pathologies; and different papers on phonetics, speech and linguistic analysis, pragmatics and sociolinguistics. Many papers are also dedicated to speech and second language studies. The online publication with FUP allows direct access to sound and video linked to papers (when downloaded)