G0^0 Electronics and Data Acquisition (Forward-Angle Measurements)

The G$^0$ parity-violation experiment at Jefferson Lab (Newport News, VA) is designed to determine the contribution of strange/anti-strange quark pairs to the intrinsic properties of the proton. In the forward-angle part of the experiment, the asymmetry in the cross section was measured for $\vec{e}p$ elastic scattering by counting the recoil protons corresponding to the two beam-helicity states. Due to the high accuracy required on the asymmetry, the G$^0$ experiment was based on a custom experimental setup with its own associated electronics and data acquisition (DAQ) system. Highly specialized time-encoding electronics provided time-of-flight spectra for each detector for each helicity state. More conventional electronics was used for monitoring (mainly FastBus). The time-encoding electronics and the DAQ system have been designed to handle events at a mean rate of 2 MHz per detector with low deadtime and to minimize helicity-correlated systematic errors. In this paper, we outline the general architecture and the main features of the electronics and the DAQ system dedicated to G$^0$ forward-angle measurements.Comment: 35 pages. 17 figures. This article is to be submitted to NIM section A. It has been written with Latex using \documentclass{elsart}. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment In Press (2007

A 64-channel personal computer based image reconstruction system and applications in single echo acquisition magnetic resonance elastography and ultra-fast magnetic resonance imaging.

Emerging technologies in parallel magnetic resonance imaging (MRI) with massive receiver arrays have paved the way for ultra-fast imaging at increasingly high frame rates. With the increase in the number of receiver channels used to implement parallel imaging techniques, there is a corresponding increase in the amount of data that needs to be processed, slowing down the process of image reconstruction. To develop a complete reconstruction system which is easy to assemble in a single computer for a real-time rendition of images is a relevant challenge demanding dedicated resources for high speed digital data transfer and computation. We have enhanced a 64 channel parallel receiver system designed for single echo acquisition (SEA) MRI into a real-time imaging system by interfacing it with two commercially available digital signal processor (DSP) boards which are capable of transferring large amounts of digital data via a dedicated bus from two high performance digitizer boards. The resulting system has been used to demodulate raw image data in real-time data and store them at rates of 200 frames per second (fps) and subsequently display the processed data at rates of 26 fps. A further interest in realtime reconstruction techniques is to reduce the data handling issues. Novel ways to minimize the digitized data are presented using reduced sampling rate techniques. The proposed techniques reduce the amount of data generated by a factor of 5 without compromising the SNR and with no additional hardware. Finally, the usability of this tool is demonstrated by investigating fast imaging applications. Of particular interest among them are MR elastography applications. An exploratory study of SEA MRE was done to study the temperature dependency of shear stiffness in an agarose gel and the results correlate well with existing literature. With the ability to make MRE images in a single echo, the SEA MRE technique has an advantage over the conventional MRE techniques

FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator

Spiking Neural Networks (SNNs) are expected to be a promising alternative to Artificial Neural Networks (ANNs) due to their strong biological interpretability and high energy efficiency. Specialized SNN hardware offers clear advantages over general-purpose devices in terms of power and performance. However, there's still room to advance hardware support for state-of-the-art (SOTA) SNN algorithms and improve computation and memory efficiency. As a further step in supporting high-performance SNNs on specialized hardware, we introduce FireFly v2, an FPGA SNN accelerator that can address the issue of non-spike operation in current SOTA SNN algorithms, which presents an obstacle in the end-to-end deployment onto existing SNN hardware. To more effectively align with the SNN characteristics, we design a spatiotemporal dataflow that allows four dimensions of parallelism and eliminates the need for membrane potential storage, enabling on-the-fly spike processing and spike generation. To further improve hardware acceleration performance, we develop a high-performance spike computing engine as a backend based on a systolic array operating at 500-600MHz. To the best of our knowledge, FireFly v2 achieves the highest clock frequency among all FPGA-based implementations. Furthermore, it stands as the first SNN accelerator capable of supporting non-spike operations, which are commonly used in advanced SNN algorithms. FireFly v2 has doubled the throughput and DSP efficiency when compared to our previous version of FireFly and it exhibits 1.33 times the DSP efficiency and 1.42 times the power efficiency compared to the current most advanced FPGA accelerators