High performance Tunnel Field Effect Transistors based on in-plane transition metal dichalcogenide heterojunctions

In-plane heterojunction tunnel field effect transistors based on monolayer transition metal dichalcogenides are studied by means of self-consistent non-equilibrium Green's functions simulations and an atomistic tight-binding Hamiltonian. We start by comparing several heterojunctions before focusing on the most promising ones, i.e WTe2-MoS2 and MoTe2-MoS2. The scalability of those devices as a function of channel length is studied, and the influence of backgate voltages on device performance is analysed. Our results indicate that, by fine-tuning the design parameters, those devices can yield extremely low sub-threshold swings (below 5mV/decade) and Ion/Ioff ratios higher than 1e8 at a supply voltage of 0.3V, making them ideal for ultra-low power consumption.Comment: 10 page

Scaling Properties of Ge-SixGe1-x Core-Shell Nanowire Field Effect Transistors

We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/OFF current ratio.Comment: 5 pages, 4 figures. IEEE Transactions on Electron Devices (in press

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime

The intermediate transport regime in nanoscale transistors between the fully ballistic case and the quasi equilibrium case described by the drift-diffusion model is still an open modeling issue. Analytical approaches to the problem have been proposed, based on the introduction of a backscattering coefficient, or numerical approaches consisting in the MonteCarlo solution of the Boltzmann transport equation or in the introduction of dissipation in quantum transport descriptions. In this paper we propose a very simple analytical model to seamlessly cover the whole range of transport regimes in generic quasi-one dimensional field-effect transistors, and apply it to silicon nanowire transistors. The model is based on describing a generic transistor as a chain of ballistic nanowire transistors in series, or as the series of a ballistic transistor and a drift-diffusion transistor operating in the triode region. As an additional result, we find a relation between the mobility and the mean free path, that has deep consequences on the understanding of transport in nanoscale devices