3 research outputs found

    Defect-tolerance and testing for configurable nano-crossbars

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    Moore\u27s Law speculated a trend in computation technology in terms of number of transistors per unit area that would double roughly every two years. Even after 40 years of this prediction, current technologies have been following it successfully. There are however, certain physical limitations of current CMOS that would result in fundamental obstructions to continuation of Moore\u27s Law. Although there is a debate amongst experts on how much time it would take for this to happen, it is certain that some entirely new paradigms for semiconductor electronics would be needed to replace CMOS and to delay the end of Moore\u27s Law. Silicon nanowires (SiNW) and Carbon nanotubes (CNT) possess significant promise to replace current CMOS --Abstract, page iv

    Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

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    Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

    Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance

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    Emerging nanoelectronics are expected to have very high manufacturetime defect rates and operation-time fault rates. Traditional N-modular redundancy (NMR) exploits the large device densities offered by these nanoelectronics to tolerate these high fault rates by allocating redundant resources according to the worst case fault rates. However, this approach is inflexible when the fault rates are time varying. In this paper, we propose a dynamically adaptive NMR approach by developing: (i) a genre of nanofabric topologies that supports sharing of redundancies in the NMR approach so as to adapt to the time varying fault rates and (ii) reconfiguration algorithms for these topologies to deal with fault tolerance loss caused by manufacturing defects and operation-time online faults, respectively. Simulation results verify that the ability to construct reliable systems, possibly the paramount consideration in constructing working applications in nanoelectronics, is significantly improved with the proposed flexible NMR architecture and the reconfiguration algorithms
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