1,067 research outputs found
CMOL: Second Life for Silicon?
This report is a brief review of the recent work on architectures for the
prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including
digital memories, reconfigurable Boolean-logic circuits, and mixed-signal
neuromorphic networks. The basic idea of CMOL circuits is to combine the
advantages of CMOS technology (including its flexibility and high fabrication
yield) with the extremely high potential density of molecular-scale
two-terminal nanodevices. Relatively large critical dimensions of CMOS
components and the "bottom-up" approach to nanodevice fabrication may keep CMOL
fabrication costs at affordable level. At the same time, the density of active
devices in CMOL circuits may be as high as 1012 cm2 and that they may provide
an unparalleled information processing performance, up to 1020 operations per
cm2 per second, at manageable power consumption.Comment: Submitted on behalf of TIMA Editions
(http://irevues.inist.fr/tima-editions
Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits
In nanoelectronic circuit synthesis, the majority gate and the inverter form
the basic combinational logic primitives. This paper deduces the mathematical
formulae to estimate the logical masking capability of majority gates, which
are used extensively in nanoelectronic digital circuit synthesis. The
mathematical formulae derived to evaluate the logical masking capability of
majority gates holds well for minority gates, and a comparison with the logical
masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and
XOR/XNOR is provided. It is inferred from this research work that the logical
masking capability of majority/minority gates is similar to that of XOR/XNOR
gates, and with an increase of fan-in the logical masking capability of
majority/minority gates also increases
From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula
Š 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that
more and more transistors can be built into the same chip area to make VLSI more
and more powerful in its functions. As the typical feature size of CMOS VLSI is
shrunk into deep submicron domain, nanotechnology is the next step in order to
maintain Mooreâs law for several more decades. Nanotechnology not only further
improves the resolution in traditional photolithography process, but also introduces
many brand-new fabrication strategies, such as bottom-up molecular self-assembly.
Nanotechnology is also enabling many novel devices and circuit architectures which
are totally different from current microelectronics circuits, such as quantum
computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is
bringing another technology revolution to traditional CMOS VLSI technology. In
order to train students to meet the quickly-increasing industry demand for nextgeneration
nanoelectronics engineers, we are making efforts to introduce
nanotechnology into our VLSI curricula. We have developed a series of VLSI
curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power
VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing,
etc. Furthermore, we developed a series of micro and nanotechnology related courses,
such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 â
MEMS (Microelectromechanical Systems). We introduce nanotechnology into our
VLSI curricula, and teach the students about various devices, fabrication processes,
circuit architectures, design and simulation skills for future nanotechnology-based
nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture,
carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum
computing, bioelectronic circuits, etc. Students show intense interest in these exciting
topics. Some students also choose nanoelectronics as the topic for their master
project/thesis, and perform successful research in the field. The program has attracted
many graduate students into the field of nanoelectronics
A Compact CMOS Memristor Emulator Circuit and its Applications
Conceptual memristors have recently gathered wider interest due to their
diverse application in non-von Neumann computing, machine learning,
neuromorphic computing, and chaotic circuits. We introduce a compact CMOS
circuit that emulates idealized memristor characteristics and can bridge the
gap between concepts to chip-scale realization by transcending device
challenges. The CMOS memristor circuit embodies a two-terminal variable
resistor whose resistance is controlled by the voltage applied across its
terminals. The memristor 'state' is held in a capacitor that controls the
resistor value. This work presents the design and simulation of the memristor
emulation circuit, and applies it to a memcomputing application of maze solving
using analog parallelism. Furthermore, the memristor emulator circuit can be
designed and fabricated using standard commercial CMOS technologies and opens
doors to interesting applications in neuromorphic and machine learning
circuits.Comment: Submitted to International Symposium of Circuits and Systems (ISCAS)
201
Recommended from our members
Nanowire nanocomputer as a finite-state machine
Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly-organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine (nanoFSM). The system was fabricated using a design- oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoFSM through modular design employing a multi-tile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoFSM integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive inter-tile and intra-tile communication that exhibits rigorous input/output (I/O) matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a FSM or computer. The programmable multi-tile circuit was also re-programmed to a functionally-distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our new design-oriented deterministic methodology to yield more extensive multi-tile systems, suggest that proposed general-purpose nanocomputers can be realized in the near future.Chemistry and Chemical BiologyEngineering and Applied Science
- âŚ