Quarc: a novel network-on-chip architecture

This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast. We present the topology, routing discipline and switch architecture for the Quarc NoC and demonstrate the performance with the results obtained from discrete event simulations

Fast, Accurate and Detailed NoC Simulations

Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy

Endogenous N-nitroso compounds, and their precursors, present in bacon, do not initiate or promote aberrant crypt foci in the colon of rats

Processed meat intake is associated with increased risk of colorectal cancer. This association may be explained by the endogenous formation of N-nitroso compounds (NOC). The hypothesis that meat intake can increase fecal NOC levels and colon carcinogenesis was tested in 175 Fischer 344 rats. Initiation was assessed by the number of aberrant crypt foci (ACF) in the colon of rats 45 days after the start of a high-fat bacon-based diet. Promotion was assessed by the multiplicity of ACF (crypts per ACF) in rats given experimental diets for 100 days starting 7 days after an azoxymethane injection. Three promotion studies were done, each in 5 groups of 10 rats, whose diets contained 7%, 14%, or 28% fat. Tested meats were bacon, pork, chicken, and beef. Fecal and dietary NOC were assayed by thermal energy analysis. Results show that feces from rats fed bacon-based diets contained 10-20 times more NOC than feces from control rats fed a casein-based diet (all p < 0.0001 in 4 studies). In bacon-fed rats, the amount of NOC input (diet) and output (feces) was similar. Rats fed a diet based on beef, pork, or chicken meat had less fecal NOC than controls (most p < 0.01). No ACF were detected in the colon of bacon-fed uninitiated rats. After azoxymethane injection, unprocessed but cooked meat-based diets did not change the number of ACF or the ACF multiplicity compared with control rats. In contrast, the bacon-based diet consistently reduced the number of large ACF per rat and the ACF multiplicity in the three promotion studies by 12%, 17%, and 20% (all p < 0.01). Results suggest that NOC from dietary bacon would not enhance colon carcinogenesis in rats

Quarc: a high-efficiency network on-chip architecture

The novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC. This paper provides an ASIC implementation of both architectures using UMCpsilas 0.13 mum CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs

An analytical performance model for the Spidergon NoC

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator

Energy Model of Networks-on-Chip and a Bus

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC link

A performance model of communication in the quarc NoC

Networks on-chip (NoC) emerged as a promising communication medium for future MPSoC development. To serve this purpose, the NoCs have to be able to efficiently exchange all types of traffic including the collective communications at a reasonable cost. The Quarc NoC is introduced as a NOC which is highly efficient in performing collective communication operations such as broadcast and multicast. This paper presents an introduction to the Quarc scheme and an analytical model to compute the average message latency in the architecture. To validate the model we compare the model latency prediction against the results obtained from discrete-event simulations