FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Efficient Dual Output Regulating Rectifier and Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power Transfer †

A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology

Design of a Monostable for the controller of an innovative Buck regulator

In this work a monostable circuit, implemented in 90nm CMOS technology for Texas Instruments, is presented. A high efficiency Buck converter is used in the Power Management Module of a very low-power microcontroller and the monostable is the main part of the Buck's controller. Various solutions have been investigated for the monostable realization, in order to achieve the lowest current consumption possibl