2,016 research outputs found
Students’ acceptance towards kahoot application in mastering culinary terminology
Kahoot! is a game-based learning platform used to review students’ knowledge, for formative assessment and provides an opportunity not only to assess students' conceptual understanding but also to build new knowledge through further clarification during or after the game. The objective of this study is to assess the acceptability of culinary students in the use of Kahoot! application for mastery the culinary terminology. This study aimed to identify students' acceptance of learning applications, to identify students' acceptance of Kahoot! use in terms of memory as well as students' level of mastering Kahoot! in the learning process. This study is a descriptive study that used a five-point Likert scale questionnaire as an instrument. A total of 48 second year students from the Catering program were used as the study sample. The collected data were analyzed using Statistical Package for Social Science Version 23.0 for Windows (SPSS). The results show that the aspect of students' level of mastering the culinary terminology using Kahoot! application is high with a mean score of 4.55. Whereas the students’ acceptance of Kahoot! as a learning application, was also high with a mean score of 4.44. Finally, the students’ acceptance of the culinary terminology tested using Kahoot! is high with a mean score of 4.45
Parametrization of the radiation induced leakage current increase of NMOS transistors
The increase of the leakage current of NMOS transistors during exposure to
ionizing radiation is known and well studied. Radiation hardness by design
techniques have been developed to mitigate this effect and have been
successfully used. More recent developments in smaller feature size
technologies do not make use of these techniques due to their drawbacks in
terms of logic density and requirement of dedicated libraries. During operation
the resulting increase of the supply current is a serious challenge and needs
to be considered during the system design.
A simple parametrization of the leakage current of NMOS transistors as a
function of total ionizing dose is presented. The parametrization uses a
transistor transfer characteristics of the parasitic transistor along the
shallow trench isolation to describe the leakage current of the nominal
transistor. Together with a parametrization of the number of positive charges
trapped in the silicon dioxide and number of activated interface traps in the
silicon to silicon dioxide interface the leakage current as a function of the
exposure time to ionizing radiation results. This function is fitted to data of
the leakage current of single transistors as well as to data of the supply
current of full ASICs.Comment: 8 pages, 10 figure
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
Research on low power technology by AC power supply circuits
制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit
Ultra low power adiabatic logic using diode connected DC biased PFAL logic
With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family
Robustness of Power Analysis Attack Resilient Adiabatic Logic: WCS-QuAL under PVT Variations
In this paper, we propose Without Charge Sharing
Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure
against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of % Normalized Energy Deviation (NED) and % Normalized Standard Deviation (NSD) at all simulated frequencies. Also, all 2-input gates using WCS-QuAL dissipate nearly equal energy for all possible input transitions. In addition, the energy dissipated
by WCS-QuAL approaches to the energy dissipation of EESPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance, GF (24) bit-parallel multiplier was implemented as a design example. The impact of Process-Voltage-Temperature (PVT) variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT
variations and when the power supply is scaled down compared to EE-SPFAL and SPGAL. At lower technology, WCS-QuAL, shows more improvement in energy dissipation than EE-SPFAL
IDPAL - Input Decoupled Partially Adiabatic Logic: Implementation and Examination
This thesis presents the experimental results of a four-phase IDPAL eight-input exclusive-OR gate. The following problems with IDPAL are addressed: multistage circuits malfunctioning, simulation convergence anomalies, and inferring input information through the power clock current. EPAD MOSFETs, which provide a low threshold voltage, are shown to be unsuccessful in correcting the malfunctioning behavior of multilayer circuits. A solution to multilayer IDPAL circuits malfunctioning, called IDPAL with discharge, is shown. The differences between simulation waveforms produced by LTspice and the experimental circuits recorded by a Tektronix’s Oscilloscope are investigated. IDPAL is implemented and analyzed using ALD MOSFETs for the following adiabatic families: 2N-2P, IDPAL, and IDPAL with discharge
Layout Design and Implementation of Adiabatic based Low Power CPAL Ripple Carry Adder
his paper presents schematic and layout design s for low power adiabatic Ripple Carry Adder which is implemented by proposed N - type & P - type Full Adder Cell . Adiabatic logic Design is the most efficient energy saving technique which provides very low power dis sipat ion for VLSI circuits. In this paper the main emphasis on the most significant technique of adiabatic logic design that is Complementary Pass Transistor Logic. Simulation results show s that energy loss of digital VLSI circuits can be greatly reduced by using Complementary Pass Transistor A diabatic Logic technique. All the circuits have been simulated on BSIM3V3 90nm technology on tanner EDA tool
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