NISC-based universal soft-input soft-output demapper

International audienceApplications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints, but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. Application Specific Instruction-set Processor (ASIP) design approach is key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions which generally leads to an overhead related to instruction decoding. No-Instruction-Set-Computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this paper, the NISC approach is explored through a casestudy design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-of-the-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters