User Antennas

The following subject areas are covered: (1) impact of frequency change of user and spacecraft antenna gain and size; (2) basic personal terminal antennas (impact of 20/30 GHz frequency separation; parametric studies - gain, size, weight; gain and figure of merit (G/T); design data for selected antenna concepts; critical technologies and development goals; and recommendations); and (3) user antenna radiation safety concerns

A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

BiCMOS Millimetre-wave low-noise amplifier

Abstract: Please refer to full text to view abstract.D.Phil. (Electrical and Electronic Engineering

Bidirectional common-path for 8-to-24 gHz low noise SiGe BiCMOS T/R module core-chip

This thesis is based on the design of an 8-to-24 GHz low noise SiGe BiCMOS Transmitter/Receiver (T/R) Module core-chip in a small area by bidirectional common-path. The next-generation phased array systems require multi-functionality and multi-band operation to form multi-purpose integrated circuits. Wide bandwidth becomes a requirement for the system in various applications, such as electronic warfare, due to leading cheaper and lighter system solutions. Although III-V technologies can satisfy the high-frequency specifications, they are expensive and have a large area. The silicon-based technologies promise high integration capability with low cost, but they sacrifice from the performance to result in desired bandwidth. The presented dissertation targets system and circuit level solutions on the described content. The wideband core-chip utilized a bidirectional common path to surpass the bandwidth limitations. The bidirectionality enhances the bandwidth, noise, gain and area of the transceiver by the removal of the repetitive blocks in the unidirectional common chain. This approach allows succeeding desired bandwidth and compactness without sacrificing from the other high-frequency parameters. The realized core-chip has 31.5 and 32 dB midband gain for the receiver and transmitter respectively, with a + 2.1 dB /GHz of positive slope. Its RMS phase and amplitude errors are lower than 5.60 and 0.8 dB, respectively for 4-bit of resolution. The receiver noise figure is lower than 5 dB for the defined bandwidth while dissipating 112 mW of power in a 5.5 mm2 area. The presented results verify the advantage of the favored architecture and might replace the III-V based counterparts

A Q-enhanced 3.6 GHz tunable CMOS bandpass filter for wideband wireless applications

With the rapid development of information technology, more and more bandwidth is required to transmit multimedia data. Since local communication networks are moving to wireless domain, it brings up great challenges for making integrated wideband wireless front-ends suitable for these applications. RF filtering is a fundamental need in all wireless front-ends and is one of the most difficult parts to be integrated. This has been a major obstacle to the implementation of low power and low cost integrated wireless terminals. Lots of previous work has been done to make integrated RF filters applicable to these applications. However, some of these filters are not designed with standard CMOS technology. Some of them are not designed in desired frequency bands and others do not have sufficient frequency bandwidth. This research demonstrates the design of a tunable wideband RF filter that operates at 3.6 GHz and can be easily changed to a higher frequency range up to 5 GHz. This filter is superior to the previous designs in the following aspects: a) wider bandwidth, b) easier to tune, c) balancing in noise and linearity, and d) using standard CMOS technology. The design employs the state-of-the-art inductor degenerated LNA, acting as a transconductor to minimize the overall noise figure. A Q-enhancement circuit is employed to compensate the loss from lossy on-chip spiral inductors. Center frequency and bandwidth tuning circuits are also embedded to make the filter suitable for multi band operations. At first, a second order bandpass filter prototype was designed in the standard 0.18 ìm CMOS process. Simulation results showed that at 3.6 GHz center frequency and with a 60-MHz bandwidth, the input third-order intermodulation product (IIP3) and input-referred 1 dB compression point (P1dB) was -22.5 dBm and -30.5 dBm respectively. The image rejection at 500 MHz away from the center frequency was 32 dB (250 MHz intermediate frequency). The Q of the filter was tunable over 3000 and the center frequency tuning range was about 150 MHz. By cascading three stages of second order filters, a sixth order filter was designed to enhance the image rejection ability and to extend the filter bandwidth. The sixth order filter had been fabricated in the standard 0.18 ìm CMOS process using 1.8-V supply. The chip occupies only 0.9 mm 0.9 mm silicon area and has a power consumption of 130-mW. The measured center frequency was tunable from 3.54 GHz to 3.88 GHz, bandwidth was tunable from 35 MHz to 80 MHz. With a 65 MHz bandwidth, the filter had a gain of 13 dB, an IIP3 of -29 dBm and a P1dB of -46 dBm

Designing of Low Power RF-Receiver Front-end with CMOS Technology

This thesis studies how to design ultra low power radio-receiver front-end circuit consisting of a low-noise CMOS amplifier and mixer for low power Bluetooth applications. This system is designed in 65-nm CMOS technology with the voltage source of 1.2 V, and it operates at 2.4 GHz. This research project includes the design of radio frequency integrated circuit with CMOS technology using CAD software for circuit design, layout design, pre and post-layout simulations. Firstly, brief study about both Low noise amplifier (LNA) and mixer has been done, and then the design structure such as, input matching network of LNA, noise of system, gain and linearity have been discussed. Later, next section reports simulation results of LNA, mixer and eventually their combination. Furthermore, the effect of packaging and non-ideal on-chip circuit performance has been considered and shown in comparison tables for more clarity. Finally, after the layout design, the obtained results of both post-layout and pre-layout simulations are compared and shown the stability of the design with parasitics consideration

Design and Analysis of SiGe Millimeter-Wave Radio Front-End MMICs For 5G Communication

This thesis focuses on design and realization of millimeter-wave radio frontend circuits for fifth generation(5G) wireless communication in 0.13um silicongermanium(SiGe) BiCMOS process. Radio front-end includes single-pole doublethrough (SPDT) switch, low noise amplifier (LNA) and buffer amplifier(BA) as a part of radio frequency(RF) transceiver system for E-band. The SPDT switch utilizes the reveres saturated SiGe heterojunction bipolar transistor(HBT). The resulting reverse saturated switch shows an insertion loss of 1 dB , isolation of 26 dB, reflection coefficient better than 25 dB at 75 GHz and provides a bandwidth of 40 GHz. A single to differential ended low noise amplifier(LNA)is designed using transformer balun. Simultaneous noise and impedance matching is used in order to realize both low noise and low reflection at the same time. The post layout simulation of E-band low noise amplifier exhibits a gain and noise figure(NF) of 26 dB and 5.5 dB respectively with a power consumption of 33.5 mW. The buffer amplifier shows a gain of 5.5 dB at 75 GHz. Finally, the receiver achieved a gain of 19.6 dB, noise figure(NF) of 6.9 dB and impedance matching better than 13.5 dB at 75 GHz. A 3 dB bandwidth of more than 12 GHz is achieved from the receiver. Extensive simulation results showing the performance of each circuit of receiver are presented