Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier degradation of transistors through consistent aging-parameter extractions for circuit simulation. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the V GS ratio is emphasized during practical case studies on CMOS inverter chains and a dynamic random access memory (DRAM) word-line circuit. Negative bias temperature instability (NBTI) mechanisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) framework. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, Δ N it with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si–H bond breakage is also proven by the quantifying R-D simulation. From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions and therefore prevents further breakage of Si–H bonds in the silicon-oxide interfaces

A COMPARATIVE STUDY OF RELIABILITY FOR FINFET

The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. The emergence of FinFET technology has brought with it the same reliability issues as standard CMOS with the addition of a new prominent degradation mechanism. The same mechanisms still exist as for previous CMOS devices, including Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Electro-migration (EM), and Body Effects. A new and equally important reliability issue for FinFET is the Self -heating, which is a crucial complication since thermal time-constant is generally much longer than the transistor switching times. FinFET technology is the newest technological paradigm that has emerged in the past decade, as downscaling reached beyond 20 nm, which happens also to be the estimated mean free path of electrons at room temperature in silicon. As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology. This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms to fit to a comprehensive aging model

Two dimensional quantum and reliability modelling for lightly doped nanoscale devices

The downscaling of MOSFET devices leads to well-studied short channel effects and more complex quantum mechanical effects. Both quantum and short channel effects not only alter the performance but they also affect the reliability. This continued scaling of the MOS device gate length puts a demand on the reduction of the gate oxide thickness and the substrate doping density. Quantum mechanical effects give rise to the quantization of energy in the conduction band, which consequently creates a larger effective bandgap and brings a displacement of the inversion layer charge out of the Si/SiO2 interface. Such a displacement of charge is equivalent to an increase in the effective oxide layer thickness, a growth in the threshold voltage, and a decrease in the current level. Therefore, using the classical analysis approach without including the quantum effects may lead to perceptible errors in the prognosis of the performance of modern deep submicron devices. In this work, compact Verilog-A compatible 2D models including quantum short channel effects and confinement for the potential, threshold voltage, and the carrier charge sheet density for symmetrical lightly doped double-gate MOSFETs are developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from analytical 2D Poisson and 1D Schrodinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models were further enhanced to include negative bias temperature instability (NBTI) in order to assess the reliability of the device. NBTI effects incorporated into the models constitute interface state generation and hole-trapping. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7nm; very good agreement within ±5% has been observed for silicon thicknesses ranging from 3nm to 20nm at 1 GHz operation after 10 years

핀펫 소자에서의 핫캐리어 신뢰성 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 신형철.CMOS 로직 소자는 퍼포먼스를 향상시키기 위해 지속적으로 축소화 되고 있다. 하지만 구조 파라미터들의 축소화에 비해 동작 전압은 충분히 감소하지 않는다. 따라서 소자 내 수직 전계나 온도가 증가하는 추세이기 때문에 신뢰성은 계속해서 문제가 되고 있다. 최근 3D 소자의 신뢰성에 대한 연구는 많이 진행되고 있지만 empirical 모델링과 관련된 연구가 대부분이다. 따라서 본 연구에서는 실제 측정을 기반으로 시뮬레이션을 이용하여 물리적 이론 중심으로 로직 소자의 핫캐리어 신뢰성을 분석하였다. 먼저 핫캐리어 모델의 정확성을 향상시키기 위해서 TCAD 시뮬레이션에 electron-electron scattering을 적용하였다. 추가적으로 3D FinFET의 측정 데이터와 calibration을 진행하여 모델의 정합성을 확인하였다. calibration 과정에서는 모든 scattering 메커니즘을 고려하기 위해 다양한 전압과 온도 조건이 필요하다. 따라서 다양한 전압 조건에 따른 HCD를 분석하고, calibration을 진행하여 HCD 모델의 파라미터를 추출하였다. 다음으로 전압 조건에 따른 HCD의 온도 경향성을 분석하였다. oxide trap과 달리 interface trap은 전압 조건에 따라 다른 온도 경향성을 보인다. 따라서 interface trap을 3가지 성분으로 분리하여 각 성분의 온도 경향성을 분석하였다. Multiple particle process(MP)과 field enhanced thermal degradation process(FP)는 전압 조건과 상관없이 일정한 온도 경향성을 가진다. 반면 Single particle process(SP)는 scattering의 영향을 받기 때문에 온도 경향성은 전압 조건에 따라 달라진다. 온도 경향성 분석 과정에서도 calibration을 진행하며 여러 번의 iteration을 통해 다양한 전압 및 온도가 고려된 파라미터를 추출한다. 추출된 파라미터를 적용한 시뮬레이션 모델은 기존의 모델보다 더 정확하게 HCD 측정 결과를 예측하였다. 결과적으로 물리적 이론에 근거하여 시뮬레이션 모델 구축함으로써 HCD 분석의 정확성을 향상시켰다. 하지만 가속 조건과 동작 조건의 self-heating 효과가 다르기 때문에 소자가 실제 CMOS 회로의 동작 조건에서 interface trap을 발생시키는 메커니즘은 다를 수 있다. 따라서 우리는 동작 영역에서의 각 성분의 비율까지 예측하였다. 마지막으로 우리는 10 nm node 소자에서 nFinFET에 비해 pFinFET에서 높은 열화가 발생하는 원인에 대해 분석하였다. pFinFET은 소스/드레인 물질로 SiGe를 사용하기 때문에 nFinFET에 비해 self-heating 효과가 심하여 소자 온도가 도 높다. 이론적으로 MP 메커니즘의 lifetime은 온도가 증가할수록 감소하기 때문에 MP에 의한 열화 또한 감소한다. 따라서 소자 온도가 더 높은 pFinFET에서 nFinFET에 비해 더 많은 MP가 발생하기 어렵다. 하지만 nFinFET 과 달리 pFinFET에서는 Si-H bond의 electron과 hole이 반응하여 interface trap을 생성시키는 RD 가 발생할 수 있다. 또한 RD는 온도가 높을수록 더 많은 열화가 발생하기 때문에, pFinFET에서 nFinFET보다 더 많은 열화가 발생하는 현상을 설명할 수 있다. 따라서 우리는 HCD 조건이지만 소자 온도가 높은 pFinFET에서 추가적인 RD 메커니즘이 발생할 수 있다고 제안한다. 다양한 전압 조건에서의 전류 열화율을 통해 주요 열화 메커니즘을 분석하였으며 pFinFET에서는 RD가 주요함을 확인하였다. 또한 TCAD 시뮬레이션을 이용하여 HCD 조건에서 발생할 수 있는 RD를 예측하였다. 그 결과 RD를 제외한 순수 hot carrier 성분은 pFinFET보다 nFinFET에서 더 많이 발생한다.CMOS logic devices have been scaled down to improve performance. However, the operating voltage is not sufficiently reduced compared to the scale down in physical dimensions. Therefore, since the electric field and temperature of the device gradually increase, reliability is still a critical issue in logic devices. Recently, many studies on the reliability of 3D devices are being conducted, but most of the studies are related to empirical modeling. Therefore, in this study, based on the actual measurement results, the hot carrier degradation(HCD) reliability of the logic device was analyzed focusing on the physical theory using Technology computer-aided design (TCAD) simulation. First, electron-electron scattering(EES) was applied to the TCAD simulation to improve the accuracy of the hot carrier model. Additionally, calibration between the measurement data of 14 nm node FinFET and the model was performed to confirm the consistency. The calibration process required various voltage and temperature conditions to account for all scattering mechanisms. Therefore, HCD was analyzed according to various voltage conditions, and the parameters of the HCD model were extracted by calibration process. Next, temperature dependence under various HCD conditions was analyzed. Unlike oxide traps, interface traps show different temperature dependence depending on HCD voltage conditions. Therefore, the interface traps were separated into three components and the temperature dependence was analyzed for each component. Multiple particle process (MP) and Field enhanced thermal degradation process (FP) have a constant temperature dependence regardless of voltage conditions. On the other hand, the temperature dependence of Single particle process (SP) varies depending on the voltage condition because SP is affected by scattering. In the process of temperature dependence analysis, calibration is also performed and parameters considering various voltages and temperatures were extracted through several iterations. The improved model to which the extracted parameters were applied showed more precise prediction of degradation compared to that of the previous model. As a results, accuracy of the HCD analysis was improved by establishing the HCD simulation framework based on physical theories. However, since the self-heating effect of the acceleration condition and the operation condition are different, the HCD mechanism that occurs in the actual CMOS circuit may also be different. Therefore, we predicted the ratio of each component under operating condition. Finally, in 10 nm node devices, we analyzed the cause of higher HCD in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain material which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle(MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the HCD mechanisms to occur more in pFinFETs which has higher temperature than nFinFETs. However, in pFinFETs unlike nFinFETs, reaction-diffusion (RD) mechanism can occur in which holes react with the electrons of Si-H bonds to generate interface traps. Also, since RD deteriorates more as the temperature increases, the phenomenon that more degradation occurs in pFinFET than nFinFET can be explained by the RD mechanism. Therefore, we propose an additional RD mechanism that is caused by high device temperature in pFinFETs even in HCD condition. Main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that RD is dominant in pFinFETs. Also, RD that can occur in HCD condition was predicted through TCAD simulation. As a results, degradation due to pure hot carriers without RD occurs more in nFinFETs than in pFinFETs.Abstract i Chapter 1. Introduction 1 Chapter 2. Hot Carrier Degradation Model 4 2.1. Physical theory 4 2.2. TCAD simulation 8 2.3. Calibration process 14 2.4. Summary 22 Chapter 3. Analysis on Temperature Dependence of HCD 25 3.1. Introduction 25 3.2. Temperature dependence according to acceleration conditions 26 3.3. Calibration process 30 3.4. Mechanism separation 33 3.5. HCD prediction in the nominal voltage 35 3.6. Summary 36 Chapter 4. Comparative Analysis of HCD in nMOS/pMOS FinFET 39 4.1. Introduction 39 4.2. Comparison of HCD in the long/short channel FinFET 40 4.3. Self-heating effect in n/pFinFET 44 4.4. Bias Temperature Instability(BTI) in n/pFinFET 47 4.5. Summary 59 Chapter 5. Conclusion 64 Abstract in Korean 66 List of Publications 69Docto

3-D statistical simulation comparison of oxide reliability of planar MOSFETs and FinFET

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. © 2013 IEEE.published_or_final_versio

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation

The focus of this thesis is on the development and implementation of aging-aware design methods, which are suitable to satisfy current needs of analog circuit design. Based on the well known \gm/\ID sizing methodology, an innovative tool-assisted aging-aware design approach is proposed, which is able to estimate shifts in circuit characteristics using mostly hand calculation schemes. The developed concept of an operating point-dependent degradation leads to the definition of an aging-aware sensitivity, which is compared to currently available degradation simulation flows and proves to be efficient in the estimation of circuit degradation. Using the aging-aware sensitivity, several analog circuits are investigated and optimized towards higher reliability. Finally, results are presented for numerous target specifications

Characterization of self-heating effects and assessment of its impact on reliability in finfet technology

The systematically growing power (heat) dissipation in CMOS transistors with each successive technology node is reaching levels which could impact its reliable operation. The emergence of technologies such as bulk/SOI FinFETs has dramatically confined the heat in the device channel due to its vertical geometry and it is expected to further exacerbate with gate-all-around transistors. This work studies heat generation in the channel of semiconductor devices and measures its dissipation by means of wafer level characterization and predictive thermal simulation. The experimental work is based on several existing device thermometry techniques to which additional layout improvements are made in state of the art bulk FinFET and SOI FinFET 14nm technology nodes. The sensors produce excellent matching results which are confirmed through TCAD thermal simulation, differences between sensor types are quantified and error bars on measurements are established. The lateral heat transport measurements determine that heat from the source is mostly dissipated at a distance of 1µm and 1.5µm in bulk FinFET and SOI FinFET, respectively. Heat additivity is successfully confirmed to prove and highlight the fact that the whole system needs to be considered when performing thermal analysis. Furthermore, an investigation is devoted to study self-heating with different layout densities by varying the number of fins and fingers per active region (RX). Fin thermal resistance is measured at different ambient temperatures to show its variation of up to 70% between -40°C to 175°C. Therefore, the Si fin has a more dominant effect in heat transport and its varying thermal conductivity should be taken into account. The effect of ambient temperature on self-heating measurement is confirmed by supplying heat through thermal chuck and adjacent heater devices themselves. Motivation for this work is the continuous evolution of the transistor geometry and use of exotic materials, which in the recent technology nodes made heat removal more challenging. This poses reliability and performance concerns. Therefore, this work studies the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions. Front-end-of-line (FEOL) reliability mechanisms, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB), are studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. By performing an HCI stress at moderate bias conditions, this dissertation shows that the laborious techniques of heat subtraction are no longer necessary. Self-heating is also studied at more realistic device switching conditions by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions and degradation is not distinguishable