Multistate spin-transfer-torque random access memory

Spin-transfer-torque random access memory (STT-RAM) is an emerging non-volatile memory technology that stores information as the relative alignment of two ferromagnets in a magnetic tunnel junction stack. Due to high scalability, speed and endurance STT-RAM is being considered as a promising candidate for future universal memory. To improve storage density various multi-state configurations have been proposed for STT-RAM. Previously, using micromagnetic simulations, it was shown that shape anisotropy of a cross-shaped ferromagnet can be used to achieve multi-state operation in a STT-RAM bit. In this work, we attempt to demonstrate the multi-state operation of such cross-shaped ferromagnet experimentally. We have explored different approach to fabricate cross-shaped magnetic tunnel junctions. Using magnetic force microscopy we demonstrate equilibrium magnetization states of a patterned cross-shaped ferromagnet. Challenges and future perspectives have been discussed.Electrical and Computer Engineerin

Standards for the Characterization of Endurance in Resistive Switching Devices

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products

Memristor Based Multi-State Shift Register Architecture

Bio-inspiring circuit design attracts a great deal of attention among researchers in the field of electronics. Memristor has emerged not only because of their potential use in neuromorphic circuits but also because of their feasible fabrication using low-cost techniques. This research presents the use of memristors to build multi-state shift registers. Memristors are capable of storing and processing multi-state logic and design of an architecture for their use in shift register have potential applications in bio-inspired integrated circuits, telecommunication systems, cryptology, display technologies, data storage, chaotic circuits, etc. The designed shift register consists of stages with capability to store and transfer multiple bits. The number of stages can be adjusted depending on the requirements of the specific applications. Each stage of the shift register consists of two memristors for a continuous signal generation at the output of each stage. Reading and writing are executed in sequential order so that when reading operation is performed by a memristor, new data is transferred to another for writing. The amplitude of the voltage corresponds to the logic state and voltage levels are classified into logic states using comparators. For n-state logic, 2n-1 comparators are required at each stage. Yakopcic’s memristor model is used in the simulations conducted in LTSPICE. The multi-state shift register architecture provided in this research successfully stores and shifts the data in the desired logic state

Spatial Vector Microwave Measurement

V této práci je představena nová interferometrická měřicí metoda pro měření koeficientu přenosu mezi dvěma anténami. Jestliže je přenos mezi anténami realizován odrazem od nějakého předmětu, lze metodu využít např. pro mikrovlnné zobrazování. Navržený systém obsahuje referenční větev obsahující anténu, která přímo ozařuje přijímací anténu a testovací větev, kde anténa ozařuje testovaný objekt. Elektromagnetická vlna z testovacího kanálu je od testovacího objektu odražena do přijímací antény, kde interferuje s vlnou z referenční větve. Pro jednoznačné získání fázového posunu mezi referenční a testovací vlnou jsou provedena postupně minimálně dvě interferometrická měření, kdy je v referenčním kanálu nastaven vhodný fázový posun a amplituda přenosu. Při měření můžeme provést více nezávislých interferometrických měření a vzniklá redundance může být využita ke zmenšení nejistot měření. Dále byl popsán způsob geometrické representace měření, který umožňuje názorně odhadnout nejisty měření. Nejistoty měření byly určeny i na základě numerické Monte Carlo metody. Navržená konfigurace byla ověřena jak přesným měřením za použití vektorového analyzátoru pro ověření nejistot měření, tak původní konfigurací pro ověření funkčnosti celého konceptu. Navrženou metodou bylo provedeno mikrovlnné zobrazování metodou inverzní syntetické apertury a byla tak ověřena použitelnost navrženého systému.This work presents a new interferometric measuring method for measuring the transmission coefficient between two antennas. If the transmission between the antennas is realized by a reflection from an object, the method can be used, e.g., for microwave imaging. The proposed system contains a reference branch containing an antenna that directly irradiates the receiving antenna and a test branch where the antenna irradiates the object under test. The electromagnetic wave from the test channel is reflected from the test object into the receiving antenna where it interferes with the wave from the reference channel. To achieve a unambiguous phase shift between the reference and test waves, at least two interferometric measurements are performed sequentially, with a suitable phase shift and the amplitude of the transmission being set in the reference channel. We can perform more independent interferometric measurements while redundancy can be used to reduce measurement uncertainty. Furthermore, a method of geometric representation of the measurement has been described which makes it possible to clearly estimate the measurement uncertainty. Measurement uncertainties were determined by the numerical Monte Carlo method. The proposed configuration has been verified by accurate measurements using a vector analyzer to verify measurement uncertainties, and the original configuration to verify the functionality of the entire concept. Microwave imaging using the inverse synthetic aperture method was performed to verify the usability of the proposed system

Reconfigurable three-terminal logic devices using phase-change materials

Conventional solid-state and mass storage memories (such as SRAM, DRAM and the hard disk drive HDD) are facing many technological challenges to meet the ever-increasing demand for fast, low power and cheap data storage solutions. This is compounded by the current conventional computer architectures (such as the von Neumann architecture) with separate processing and storage functionalities and hence data transfer bottlenecks and increased silicon footprint. Beyond the von Neumann computer architecture, the combination of arithmetic-logic processing and (collocally) storage circuits provide a new and promising alternative for computer systems that overcome the many limitations of current technology. However, there are many technical challenges that face the implementation of universal blocks of both logic and memory functions using conventional silicon technology (transistor-transistor logic - TTL, and complementary metal oxide semiconductors - CMOS). Phase-change materials, such as Ge2Sb2Te5 (GST), provide a potential complement or replacement to these technologies to provide both processing and, collocally, storage capability. Existing research in phase-change memory technologies focused on two-terminal non-volatile devices for different memory and logic applications due to their ability to achieve logic-resistive switching in nanosecond time scale, their scalability down to few nanometer-scale cells, and low power requirements. To perform logic functionality, current two-terminal phase-change logic devices need to be connected in series or parallel circuits, and require sequential inputs to perform the required logic function (such as NAND and NOR). In this research programme, three-terminal (3T) non-volatile phase-change memories are proposed and investigated as potential alternative logic cells with simultaneous inputs as reconfigurable, non-volatile logic devices. A vertical 3T logic device structure is proposed in this work based on existing phase-change based memory cell architecture and original concept work by Ovshinsky. A comprehensive, multi-physics finite-element model of the vertical 3T device was constructed in Comsol Multiphysics. This model solves Laplace's equation for the electric potential due to the application of voltage sources. The calculated electric potential and fields provide the Joule heating source in the device, which is used to compute the temperature distribution through solution of the heat diffusion equation, which is necessary to activate the thermally-driven phase transition process. The physically realistic and computationally efficient nucleation- growth model was numerically implemented to model the phase change and resistance change in the Ge2Sb2Te5 (GST) phase-change material in the device, which is combined with the finite- element model using the Matlab programming interface. The changes in electrical and thermal conductivities in the GST region are taken into account following the thermally activated phase transformations between the amorphous-crystalline states using effective medium theory. To determine the appropriate voltage and temperature conditions for the SET and RESET operations, and to optimise the materials and thicknesses of the thermal and heating layers in the device, comprehensive steady-state parametric simulations were carried out using the finite-element multi-physics model. Simulations of transient cycles of writing (SET) and erasing (RESET) processes using appropriate voltage pulses were then carried out on the designed vertical 3T device to study the phase transformations for practical reconfigurable logic operations. The simulations indicated excellent resistance contrast between the logic 1 and 0 states, and successfully demonstrated the feasibility of programming the logic functions of NAND and NOR gates using this 3T configuration

RESEARCH TOOLS AND THEIR USES FOR DETERMINING THE THERMAL INACTIVATION KINETICS OF SALMONELLA IN LOW-MOISTURE FOODS

The reputation of low-moisture foods as safe foods has been crumbling over the past decade due to repeated involvement in foodborne illness outbreaks. Although various pasteurization technologies exist, a majority are thermal processes and have not been well-characterized for pasteurizing low-moisture foods. In addition, the nature of a low-moisture food matrix introduces various experimental complications that are not encountered in high-moisture foods. In this dissertation, the development, building instructions, and characterization of various open source tools for studying the inactivation kinetics of microorganisms in low-moisture foods are described. The first tool is the TDT Sandwich, a dry heating device for measuring the thermal inactivation kinetics of microorganisms. The second tool is the HumidOSH, a self-contained environmental chamber for adjusting the water activity of food samples. Accompanying these tools are two studies that characterized the thermal inactivation kinetics of Salmonella and Enterococcus faecium NRRL-B2354 in whole milk powder and chia seeds. The TDT Sandwich was shown to produce thermal inactivation kinetics that are comparable with commonly used methods while also demonstrating less variation in microbial data collected with this tool. The comparison of model parameters using statistical tests of significance is discussed with the use of Monte Carlo simulations. E. faecium was shown to be a conservative surrogate to Salmonella in chia seeds. The variability between production lots of chia seeds was found to have a large impact on the inactivation kinetics of both Salmonella and E. faecium. The open source tools presented in this dissertation and the accompanying conclusions of the thermal inactivation studies can be used to accelerate scientific progress in understanding and improving the microbiological safety of low-moisture foods. Advisers: Dr. Curtis L. Weller and Dr. David D. Jone

Threshold Switching and Self-Oscillation in Niobium Oxide

Volatile threshold switching, or current controlled negative differential resistance (CC-NDR), has been observed in a range of transition metal oxides. Threshold switching devices exhibit a large non-linear change in electrical conductivity, switching from an insulating to a metallic state under external stimuli. Compact, scalable and low power threshold switching devices are of significant interest for use in existing and emerging technologies, including as a selector element in high-density memory arrays and as solid-state oscillators for hardware-based neuromorphic computing. This thesis explores the threshold switching in amorphous NbOx and the properties of individual and coupled oscillators based on this response. The study begins with an investigation of threshold switching in Pt/NbOx/TiN devices as a function device area, NbOx film thickness and temperature, which provides important insight into the structure of the self-assembled switching region. The devices exhibit combined threshold-memory behaviour after an initial voltage-controlled forming process, but exhibit symmetric threshold switching when the RESET and SET currents are kept below a critical value. In this mode, the threshold and hold voltages are shown to be independent of the device area and film thickness, and the threshold power, while independent of device area, is shown to decrease with increasing film thickness. These results are shown to be consistent with a structure in which the threshold switching volume is confined, both laterally and vertically, to the region between the residual memory filament and the electrode, and where the memory filament has a core-shell structure comprising a metallic core and a semiconducting shell. The veracity of this structure is demonstrated by comparing experimental results with the predictions of a resistor network model, and detailed finite element simulations. The next study focuses on electrical self-oscillation of an NbOx threshold switching device incorporated into a Pearson-Anson circuit configuration. Measurements confirm stable operation of the oscillator at source voltages as low as 1.06 V, and demonstrate frequency control in the range from 2.5 to 20.5 MHz with maximum frequency tuning range of 18 MHz/V. The oscillator exhibit three distinct oscillation regimes: sporadic spiking, stable oscillation and damped oscillation. The oscillation frequency, peak-to-peak amplitude and frequency are shown to be temperature and voltage dependent with stable oscillation achieved for temperatures up to ∼380 K. A physics-based threshold switching model with inclusion of device and circuit parameters is shown to explain the oscillation waveform and characteristic. The final study explores the oscillation dynamics of capacitively coupled Nb/Nb2O5 relaxation oscillators. The coupled system exhibits rich collective behaviour, from weak coupling to synchronisation, depending on the negative differential resistance response of the individual devices, the operating voltage and the coupling capacitance. These coupled oscillators are shown to exhibit stable frequency and phase locking states at source voltages as low as 2.2 V with MHz frequency tunable range. The numerical simulation of the coupled system highlights the role of source voltage, and circuit and device capacitance in controlling the coupling modes and dynamics

In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed

Shape-engineered ferromagnets and micromagnetic simulation techniques for spin-transfer-torque random access memory

Spin-transfer-torque random access memory (STTRAM) has received great attention as a prospective universal memory due to high speed read and write capabilities, scalability to smaller technology nodes and non-volatile data retention. Two major factors that could limit the performance of large scale STTRAM arrays are the high switching current and the stochastic switching behavior. In this work, possible routes to mitigate these issues have been explored and new techniques have been proposed to estimate the reliability of the write process. Large area of the selection transistor required to support high switching current impacts the bit storage density of an STTRAM memory array. To increase the bit storage density, a multi-state STTRAM cell employing a cross-shaped ferromagnet was proposed previously. Here, the spin-transfer-torque (STT) driven mag-netization dynamics of the cross-shaped ferromagnet is revisited. As a low power alternative, voltage controlled magnetic anisotropy (VCMA) based writing scheme is studied. Trade-offs and limitations of the VCMA-induced switching over STT are also discussed. In the next part of this dissertation, magnetic properties and magnetization process of epitaxial chromium telluride thin films have been studied. Presence of strong perpendicular magnetic anisotropy in this material makes it an attractive choice for device applications. In this work, anisotropy energies of chromium telluride thin films have been estimated from magnetization measurements. The magnetization reversal process is then studied using analytical models as well as micromagnetic simulations. The last part of this work focuses on the write error rates (WER) of STTRAM. The stochastic write process of STTRAM at finite temperatures gives rise to write errors when a bit fails to switch within the duration of the write pulse. Ultra-low WER on the scale of 10⁻⁹ or less are desired for practical applications. Micromagnetic simulations are required to capture spatially-incoherent magnetization dynamics inside a ferromagnet, which may effect the WER. In this work, using the techniques of rare event enhancement, reliable calculation of WERs to 10⁻⁹ is demonstrated while keeping the computational effort to a minimum. Employing rare-event-enhanced micromagnetic simulations, WERs of both perpendicular and in-plane STTRAM bits are calculated and effects of spatially-incoherent excitations on the WER slopes are discussed.Electrical and Computer Engineerin