3,331 research outputs found
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
Adaptive OFDM System Design For Cognitive Radio
Recently, Cognitive Radio has been proposed as a promising technology to improve spectrum utilization. A highly flexible OFDM system is considered to be a good candidate for the Cognitive Radio baseband processing where individual carriers can be switched off for frequencies occupied by a licensed user. In order to support such an adaptive OFDM system, we propose a Multiprocessor System-on-Chip (MPSoC) architecture which can be dynamically reconfigured. However, the complexity and flexibility of the baseband processing makes the MPSoC design a difficult task. This paper presents a design technology for mapping flexible OFDM baseband for Cognitive Radio on a multiprocessor System-on-Chip (MPSoC)
An Implementation of a Dual-Processor System on FPGA
In recent years, Field-Programmable Gate Arrays (FPGA) have evolved rapidly
paving the way for a whole new range of computing paradigms. On the other hand,
computer applications are evolving. There is a rising demand for a system that
is general-purpose and yet has the processing abilities to accommodate current
trends in application processing. This work proposes a design and
implementation of a tightly-coupled FPGA-based dual-processor platform. We
architect a platform that optimizes the utilization of FPGA resources and
allows for the investigation of practical implementation issues such as cache
design. The performance of the proposed prototype is then evaluated, as
different configurations of a uniprocessor and a dual-processor system are
studied and compared against each other and against published results for
common industry-standard CPU platforms. The proposed implementation utilizes
the Nios II 32-bit embedded soft-core processor architecture designed for the
Altera Cyclone III family of FPGAs
A system-level multiprocessor system-on-chip modeling framework
We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework
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