936 research outputs found
Control of discrete event systems---research at the interface of control theory and computer science
System configuration and executive requirements specifications for reusable shuttle and space station/base
System configuration and executive requirements specifications for reusable shuttle and space station/bas
Intelligent Management of Mobile Systems through Computational Self-Awareness
Runtime resource management for many-core systems is increasingly complex.
The complexity can be due to diverse workload characteristics with conflicting
demands, or limited shared resources such as memory bandwidth and power.
Resource management strategies for many-core systems must distribute shared
resource(s) appropriately across workloads, while coordinating the high-level
system goals at runtime in a scalable and robust manner.
To address the complexity of dynamic resource management in many-core
systems, state-of-the-art techniques that use heuristics have been proposed.
These methods lack the formalism in providing robustness against unexpected
runtime behavior. One of the common solutions for this problem is to deploy
classical control approaches with bounds and formal guarantees. Traditional
control theoretic methods lack the ability to adapt to (1) changing goals at
runtime (i.e., self-adaptivity), and (2) changing dynamics of the modeled
system (i.e., self-optimization).
In this chapter, we explore adaptive resource management techniques that
provide self-optimization and self-adaptivity by employing principles of
computational self-awareness, specifically reflection. By supporting these
self-awareness properties, the system can reason about the actions it takes by
considering the significance of competing objectives, user requirements, and
operating conditions while executing unpredictable workloads
A Process Algebra for Supervisory Coordination
A supervisory controller controls and coordinates the behavior of different
components of a complex machine by observing their discrete behaviour.
Supervisory control theory studies automated synthesis of controller models,
known as supervisors, based on formal models of the machine components and a
formalization of the requirements. Subsequently, code generation can be used to
implement this supervisor in software, on a PLC, or embedded microprocessor. In
this article, we take a closer look at the control loop that couples the
supervisory controller and the machine. We model both event-based and
state-based observations using process algebra and bisimulation-based
semantics. The main application area of supervisory control that we consider is
coordination, referred to as supervisory coordination, and we give an academic
and an industrial example, discussing the process-theoretic concepts employed.Comment: In Proceedings PACO 2011, arXiv:1108.145
Untangling the intricacies of thread synchronization in the PREEMPT-RT linux kernel
This article proposes an automata-based model for describing and validating the behavior of threads in the Linux PREEMPT-RT kernel, on a single-core system. The automata model defines the events and how they influence the timeline of threads' execution, comprising the preemption control, interrupt handlers, interrupt control, scheduling and locking. This article also presents the extension of the Linux trace features that enable the trace of the kernel events used in the modeling. The model and the tracing tool are used, initially, to validate the model, but preliminary results were enough to point to two problems in the Linux kernel. Finally, the analysis of the events involved in the activation of the highest priority thread is presented in terms of necessary and sufficient conditions, describing the delays occurred in this operation in the same granularity used by kernel developers, showing how it is possible to take advantage of the model for analyzing the thread wake-up latency, without any need for watching the corresponding kernel code
A thread synchronization model for the PREEMPT_RT Linux kernel
This article proposes an automata-based model for describing and validating sequences of kernel events in Linux PREEMPT_RT and how they influence the timeline of threadsβ execution, comprising preemption control, interrupt handling and control, scheduling and locking. This article also presents an extension of the Linux tracing framework that enables the tracing of kernel events to verify the consistency of the kernel execution compared to the event sequences that are legal according to the formal model. This enables cross-checking of a kernel behavior against the formalized one, and in case of inconsistency, it pinpoints possible areas of improvement of the kernel, useful for regression testing. Indeed, we describe in details three problems in the kernel revealed by using the proposed technique, along with a short summary on how we reported and proposed fixes to the Linux kernel community. As an example of the usage of the model, the analysis of the events involved in the activation of the highest priority thread is presented, describing the delays occurred in this operation in the same granularity used by kernel developers. This illustrates how it is possible to take advantage of the model for analyzing the preemption model of Linux
Discrete Event Simulations
Considered by many authors as a technique for modelling stochastic, dynamic and discretely evolving systems, this technique has gained widespread acceptance among the practitioners who want to represent and improve complex systems. Since DES is a technique applied in incredibly different areas, this book reflects many different points of view about DES, thus, all authors describe how it is understood and applied within their context of work, providing an extensive understanding of what DES is. It can be said that the name of the book itself reflects the plurality that these points of view represent. The book embraces a number of topics covering theory, methods and applications to a wide range of sectors and problem areas that have been categorised into five groups. As well as the previously explained variety of points of view concerning DES, there is one additional thing to remark about this book: its richness when talking about actual data or actual data based analysis. When most academic areas are lacking application cases, roughly the half part of the chapters included in this book deal with actual problems or at least are based on actual data. Thus, the editor firmly believes that this book will be interesting for both beginners and practitioners in the area of DES
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볡μ λͺ¨λ λ©ν°λ―Έλμ΄ ν°λ―Έλ μμ λ₯Ό ν΅ν κΈ°μ΄μ μΈ μ€νλ€μ ν΅ν΄, μ μνλ λ°©λ²λ‘ μ νλΉμ±μ 보μΈλ€.As the number of processors in a chip increases, and more functions are integrated, the system status will change dynamically due to various factors such as the workload variation, QoS requirement, and unexpected component failure. On the other hand, computation-complexity of user applications is also steadily increasingvideo and graphics applications are two major driving forces in smart mobile devices, which define the main application domain of interest in this dissertation. So, a systematic design methodology is highly required to implement such complex systems which contain dynamically changed behavior as well as computation-intensive workload that can be parallelized.
A model-based approach is one of representative approaches for parallel embedded software development. Especially, HOPES framework is proposed which is a design environment for parallel embedded software supporting the overall design steps: system specification, performance estimation, design space exploration, and automatic code generation. Distinguished from other design environments, it introduces a novel concept of programming platform, called CIC (Common Intermediate Code) that can be understood as a generic execution model of heterogeneous multiprocessor architecture. The CIC task model is based on a process network model, but it can be refined to the SDF (Synchronous Data Flow) model, since it has a very desirable features for static analyzability as well as parallel processing. However, the SDF model has a typical weakness of expression capability, especially for the system-level specification and dynamically changed behavior of an application.
To overcome this weakness, in this dissertation, we propose an extended CIC task model based on dataflow and FSM models to specify the dynamic behavior of the system distinguishing inter- and intra-application dynamism. At the top-level, each application is specified by a dataflow task and the dynamic behavior is modeled as a control task that supervises the execution of applications. Inside a dataflow task, it specifies the dynamic behavior using a similar way as FSM-based SADFan SDF task may have multiple behaviors and a tabular specification of an FSM, called MTM (Mode Transition Machine), describes the mode transition rules for the SDF graph. We call it to MTM-SDF model which is classified as multi-mode dataflow models in the dissertation. It assumes that an application has a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. It enables us to perform compile-time scheduling of each graph to maximize the throughput varying the number of allocated processors, and store the scheduling information.
Also, a multiprocessor scheduling technique is proposed for a multi-mode dataflow graph. While there exist several scheduling techniques for multi-mode dataflow models, no one allows task migration between modes. By observing that the resource requirement can be additionally reduced if task migration is allowed, we propose a multiprocessor scheduling technique of a multi-mode dataflow graph considering task migration between modes. Based on a genetic algorithm, the proposed technique schedules all SDF graphs in all modes simultaneously to minimize the resource requirement. To satisfy the throughput constraint, the proposed technique calculates the actual throughput requirement of each mode and the output buffer size for tolerating throughput jitter.
For the specified task graph and scheduling results, the CIC translator generates parallelized code for the target architecture. Therefore the CIC translator is extended to support extended features of the CIC task model. In application-level, it is extended to support multiprocessor code generation for an MTM-SDF graph considering the given static scheduling results. Also, multiprocessor code generation of four different scheduling policies are supported for an MTM-SDF graph: fully-static, self-timed, static-assignment, and fully-dynamic. In system-level, the CIC translator is extended to support code generation for implementation of system request APIs and data structures for the static scheduling results and configurable task parameters.
Through preliminary experiments with a multi-mode multimedia terminal example, the viability of the proposed methodology is verified.Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Contribution 7
1.3 Dissertation organization 9
Chapter 2 Background 10
2.1 Related work 10
2.1.1 Compiler-based approach 10
2.1.2 Language-based approach 11
2.1.3 Model-based approach 15
2.2 HOPES framework 19
2.3 Common Intermediate Code (CIC) Model 21
Chapter 3 Dynamic Behavior Specification 26
3.1 Problem definition 26
3.1.1 System-level dynamic behavior 26
3.1.2 Application-level dynamic behavior 27
3.2 Related work 28
3.3 Motivational example 31
3.4 Control task specification for system-level dynamism 33
3.4.1 Internal specification 33
3.4.2 Action scripts 38
3.5 MTM-SDF specification for application-level dynamism 44
3.5.1 MTM specification 44
3.5.2 Task graph specification 45
3.5.3 Execution semantic of an MTM-SDF graph 46
Chapter 4 Multiprocessor Scheduling of an Multi-mode Dataflow Graph 50
4.1 Related work 51
4.2 Motivational example 56
4.2.1 Throughput requirement calculation considering mode transition delay 56
4.2.2 Task migration between mode transition 58
4.3 Problem definition 61
4.4 Throughput requirement analysis 65
4.4.1 Mode transition delay 66
4.4.2 Arrival curves of the output buffer 70
4.4.3 Buffer size determination 71
4.4.4 Throughput requirement analysis 73
4.5 Proposed MMDF scheduling framework 75
4.5.1 Optimization problem 75
4.5.2 GA configuration 76
4.5.3 Fitness function 78
4.5.4 Local optimization technique 79
4.6 Experimental results 81
4.6.1 MMDF scheduling technique 83
4.6.2 Scalability of the Proposed Framework 88
Chapter 5 Multiprocessor Code Generation for the Extended CIC Model 89
5.1 CIC translator 89
5.2 Code generation for application-level dynamism 91
5.2.1 Function call-style code generation (fully-static, self-timed) 94
5.2.2 Thread-style code generation (static-assignment, fully-dynamic) 98
5.3 Code generation for system-level dynamism 101
5.4 Experimental results 105
Chapter 6 Conclusion and Future Work 107
Bibliography 109
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