Design and implementation of components for renewably-powered base-stations with heterogeneous access channel

Providing high-speed broadband services in remote areas can be a challenging task, especially because of the lack of network infrastructure. As typical broadband technologies are often expensive to deploy, they require large investment from the local authorities. Previous studies have shown that a viable alternative is to use wireless base stations with high-throughput point to point (PTP) backhaul links. With base stations comes the problem of powering their systems, it is tackled in this thesis by relying on renewable energy harvesting, such as solar panels or wind turbines. This thesis, in the context of the sustainable cellular network harvesting ambient energy (SCAVENGE) project, aims to contribute to a reliable and energy efficient solution to this problem, by adjusting the design of an existing multi-radio energy harvesting base station. In Western Europe, 49 channels of 8 MHz were used for analogue TV transmissions, ranging from 470 MHz (Channel 21) to 862 MHz (Channel 69); this spectrum, now partially unused due to the digital television (DTV) switch-over, has been opened to alternative uses by the regulatory authorities. Using this newly freed ultra high frequency (UHF) range, also known as TV white space (TVWS), can offer reliable low-cost broadband access to housings and businesses in low-density areas. While UHF transmitters allow long range links, the overcrowding of the TV spectrum limits the achievable throughput; to increase the capacity of such TVWS rural broadband base station the UHF radio has previously been combined with a lower-range higher throughput GHz radio like Wireless Fidelity (WiFi). From the regulatory constraints of TVWS applications arises the need for frequency agile transceivers that observe strict spectral mask requirements, this guided previous works towards discrete Fourier transform (DFT) modulated filter-bank multicarrier (FBMC) systems. These systems are numerically efficient, as they permit the up-and-down conversion of the 40 TV channels at the cost of a single channel transceiver and the modulating transform. Typical implementations rely on power-of two fast Fourier transforms (FFTs); however the smallest transform covering the full 40 channels of the TVWS spectrum is a 64 points wide, thus involving 24 unused channels. In order to attain a more numerically-efficient implemented design, we introduce the use of mixed-radix FFTs modulating transform. Testing various sizes and architectures, this approach provides up to 6.7% of energy saving compared to previous designs. Different from orthogonal frequency-division multiplexing (OFDM), FBMC systems are generally expected to be more robust to synchronisation errors, as oversampled FBMC systems can include a guard band, and even in a doubly-dispersive channel, inter-carrier interference (ICI) can be considered negligible. Even though sub-channels can be treated independently—i.e. without the use of cross-terms—they still require equalisation. We introduce a per-band equalisation, amongst different options, a robust and fast blind approach based on a concurrent constant modulus (CM)/decision directed (DD) fractionally-space equaliser (FSE) is selected. The selected approach is capable of equalising a frequency-selective channel. Furthermore the proposed architecture is advantageous in terms of power consumption and implementation cost. After focussing on the design of the radio for TVWS transmission, we address a multi-radio user assignment problem. Using various power consumption and harvesting models for the base station, we formulate two optimisation problems, the first focuses on the base station power consumption, while the second concentrates on load balancing. We employ a dynamic programming approach to optimise the user assignment. The use of such algorithms could allow a downsizing of the power supply systems (harvesters and batteries), thus reducing the cost of the base station. Furthermore the algorithms provide a better balance between the number of users assigned to each network, resulting in a higher quality of service (QoS) and energy efficiency.Providing high-speed broadband services in remote areas can be a challenging task, especially because of the lack of network infrastructure. As typical broadband technologies are often expensive to deploy, they require large investment from the local authorities. Previous studies have shown that a viable alternative is to use wireless base stations with high-throughput point to point (PTP) backhaul links. With base stations comes the problem of powering their systems, it is tackled in this thesis by relying on renewable energy harvesting, such as solar panels or wind turbines. This thesis, in the context of the sustainable cellular network harvesting ambient energy (SCAVENGE) project, aims to contribute to a reliable and energy efficient solution to this problem, by adjusting the design of an existing multi-radio energy harvesting base station. In Western Europe, 49 channels of 8 MHz were used for analogue TV transmissions, ranging from 470 MHz (Channel 21) to 862 MHz (Channel 69); this spectrum, now partially unused due to the digital television (DTV) switch-over, has been opened to alternative uses by the regulatory authorities. Using this newly freed ultra high frequency (UHF) range, also known as TV white space (TVWS), can offer reliable low-cost broadband access to housings and businesses in low-density areas. While UHF transmitters allow long range links, the overcrowding of the TV spectrum limits the achievable throughput; to increase the capacity of such TVWS rural broadband base station the UHF radio has previously been combined with a lower-range higher throughput GHz radio like Wireless Fidelity (WiFi). From the regulatory constraints of TVWS applications arises the need for frequency agile transceivers that observe strict spectral mask requirements, this guided previous works towards discrete Fourier transform (DFT) modulated filter-bank multicarrier (FBMC) systems. These systems are numerically efficient, as they permit the up-and-down conversion of the 40 TV channels at the cost of a single channel transceiver and the modulating transform. Typical implementations rely on power-of two fast Fourier transforms (FFTs); however the smallest transform covering the full 40 channels of the TVWS spectrum is a 64 points wide, thus involving 24 unused channels. In order to attain a more numerically-efficient implemented design, we introduce the use of mixed-radix FFTs modulating transform. Testing various sizes and architectures, this approach provides up to 6.7% of energy saving compared to previous designs. Different from orthogonal frequency-division multiplexing (OFDM), FBMC systems are generally expected to be more robust to synchronisation errors, as oversampled FBMC systems can include a guard band, and even in a doubly-dispersive channel, inter-carrier interference (ICI) can be considered negligible. Even though sub-channels can be treated independently—i.e. without the use of cross-terms—they still require equalisation. We introduce a per-band equalisation, amongst different options, a robust and fast blind approach based on a concurrent constant modulus (CM)/decision directed (DD) fractionally-space equaliser (FSE) is selected. The selected approach is capable of equalising a frequency-selective channel. Furthermore the proposed architecture is advantageous in terms of power consumption and implementation cost. After focussing on the design of the radio for TVWS transmission, we address a multi-radio user assignment problem. Using various power consumption and harvesting models for the base station, we formulate two optimisation problems, the first focuses on the base station power consumption, while the second concentrates on load balancing. We employ a dynamic programming approach to optimise the user assignment. The use of such algorithms could allow a downsizing of the power supply systems (harvesters and batteries), thus reducing the cost of the base station. Furthermore the algorithms provide a better balance between the number of users assigned to each network, resulting in a higher quality of service (QoS) and energy efficiency

Toatie : functional hardware description with dependent types

Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis.Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis

Filtered Multicarrier Transmission

Orthogonal frequency‐division multiplexing (OFDM) has been adopted as the waveform of choice in the existing and emerging broadband wireless communication systems for a number of advantages it can offer. Nevertheless, investigations of more advanced multicarrier transmission schemes have continued with the aim of eliminating or mitigating its essential limitations. This article discusses multicarrier schemes with enhanced spectrum localization, which manage to reduce the spectral sidelobes of plain OFDM that are problematic in various advanced communication scenarios. These include schemes for enhancing the OFDM waveform characteristics through additional signal processing as well as filter‐bank multicarrier (FBMC) waveforms utilizing frequency‐selective filter banks instead of plain (inverse) discrete Fourier transform processing for waveform generation and demodulation.acceptedVersionPeer reviewe

Multiplierless Unified Architecture for Mixed Radix−2/3/4 FFTs

International audienceThis paper presents a novel runtime-reconfigurable, mixed radix core for computation 2−, 3−, 4− point fast Fourier transforms (FFT). The proposed architecture is based on radix-3 Wingorad Fourier transform, however multiplication is performed by constant multiplication instead of general multiplier. The complexity is equal to multiplierless 3-point FFT in terms of adders/subtractors with the exception of a few additional multiplexers. The proposed architecture supports all the FFT sizes which can be factorized into 2, 3, 4 point. It is also explained that the accuracy of the proposed architecture is not affected due to constant multiplication

Real-time Digital Signal Processing for Software-defined Optical Transmitters and Receivers

A software-defined optical Tx is designed and demonstrated generating signals with various formats and pulse-shapes in real-time. Special pulse-shapes such as OFDM or Nyquist signaling were utilized resulting in a highly efficient usage of the available fiber channel bandwidth. This was achieved by parallel data processing with high-end FPGAs. Furthermore, highly efficient Rx algorithms for carrier and timing recovery as well as for polarization demultiplexing were developed and investigated