1,519 research outputs found

    Multiple-valued Logic Operations with Universal Literals

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    We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits. A universal literal is any function on one variable. The target architecture is a sum-of-products structure, where sum is the truncated sum and product terms consist of the minimum of universal literals. A significant cost reduction is demonstrated over the conventional window literal. The proposed synthesis method starts with a sum-of-products expression. Simplification occurs as pairs of producttermsaremergedandreshaped. Weshowunder what conditions such operations can be applied.Research supported by the Natural Sciences and Engineering Research Council of Canada and by the Naval Research Laboratory, Washington, DC through direct funds at the Naval Postgraduate School, Monterey, CAResearch supported by the Natural Sciences and Engineering Research Council of Canada and by the Naval Research Laboratory, Washington, DC through direct funds at the Naval Postgraduate School, Monterey, C

    Multiple-valued operations with universal literals

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    This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Proceedings of the 24th International Symposium on Multiple-Valued Logic, May 1994, pp. 73-79, 1993We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits. A universal literal is any function on one variable. The target architecture is a sum-of-products structure, where sum is the truncated sum and product terms consist of the minimum of universal literals. A significant cost reduction is demonstrated over the conventional window literal. The proposed synthesis method starts with a sum- of products expression. Simplification occurs as pairs of product terms are merged and reshaped. We show under what conditions such operations can be applied

    Lazy Model Expansion: Interleaving Grounding with Search

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    Finding satisfying assignments for the variables involved in a set of constraints can be cast as a (bounded) model generation problem: search for (bounded) models of a theory in some logic. The state-of-the-art approach for bounded model generation for rich knowledge representation languages, like ASP, FO(.) and Zinc, is ground-and-solve: reduce the theory to a ground or propositional one and apply a search algorithm to the resulting theory. An important bottleneck is the blowup of the size of the theory caused by the reduction phase. Lazily grounding the theory during search is a way to overcome this bottleneck. We present a theoretical framework and an implementation in the context of the FO(.) knowledge representation language. Instead of grounding all parts of a theory, justifications are derived for some parts of it. Given a partial assignment for the grounded part of the theory and valid justifications for the formulas of the non-grounded part, the justifications provide a recipe to construct a complete assignment that satisfies the non-grounded part. When a justification for a particular formula becomes invalid during search, a new one is derived; if that fails, the formula is split in a part to be grounded and a part that can be justified. The theoretical framework captures existing approaches for tackling the grounding bottleneck such as lazy clause generation and grounding-on-the-fly, and presents a generalization of the 2-watched literal scheme. We present an algorithm for lazy model expansion and integrate it in a model generator for FO(ID), a language extending first-order logic with inductive definitions. The algorithm is implemented as part of the state-of-the-art FO(ID) Knowledge-Base System IDP. Experimental results illustrate the power and generality of the approach

    Minimization of Quantum Circuits using Quantum Operator Forms

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    In this paper we present a method for minimizing reversible quantum circuits using the Quantum Operator Form (QOF); a new representation of quantum circuit and of quantum-realized reversible circuits based on the CNOT, CV and CV^\dagger quantum gates. The proposed form is a quantum extension to the well known Reed-Muller but unlike the Reed-Muller form, the QOF allows the usage of different quantum gates. Therefore QOF permits minimization of quantum circuits by using properties of different gates than only the multi-control Toffoli gates. We introduce a set of minimization rules and a pseudo-algorithm that can be used to design circuits with the CNOT, CV and CV^\dagger quantum gates. We show how the QOF can be used to minimize reversible quantum circuits and how the rules allow to obtain exact realizations using the above mentioned quantum gates.Comment: 11 pages, 14 figures, Proceedings of the ULSI Workshop 2012 (@ISMVL 2012

    On Structural Parameterizations of Hitting Set: Hitting Paths in Graphs Using 2-SAT

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    Hitting Set is a classic problem in combinatorial optimization. Its input consists of a set system F over a finite universe U and an integer t; the question is whether there is a set of t elements that intersects every set in F. The Hitting Set problem parameterized by the size of the solution is a well-known W[2]-complete problem in parameterized complexity theory. In this paper we investigate the complexity of Hitting Set under various structural parameterizations of the input. Our starting point is the folklore result that Hitting Set is polynomial-time solvable if there is a tree T on vertex set U such that the sets in F induce connected subtrees of T. We consider the case that there is a treelike graph with vertex set U such that the sets in F induce connected subgraphs; the parameter of the problem is a measure of how treelike the graph is. Our main positive result is an algorithm that, given a graph G with cyclomatic number k, a collection P of simple paths in G, and an integer t, determines in time 2^{5k} (|G| +|P|)^O(1) whether there is a vertex set of size t that hits all paths in P. It is based on a connection to the 2-SAT problem in multiple valued logic. For other parameterizations we derive W[1]-hardness and para-NP-completeness results.Comment: Presented at the 41st International Workshop on Graph-Theoretic Concepts in Computer Science, WG 2015. (The statement of Lemma 4 was corrected in this update.

    One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing

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    科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9~H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

    On Generalized Records and Spatial Conjunction in Role Logic

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    We have previously introduced role logic as a notation for describing properties of relational structures in shape analysis, databases and knowledge bases. A natural fragment of role logic corresponds to two-variable logic with counting and is therefore decidable. We show how to use role logic to describe open and closed records, as well the dual of records, inverse records. We observe that the spatial conjunction operation of separation logic naturally models record concatenation. Moreover, we show how to eliminate the spatial conjunction of formulas of quantifier depth one in first-order logic with counting. As a result, allowing spatial conjunction of formulas of quantifier depth one preserves the decidability of two-variable logic with counting. This result applies to two-variable role logic fragment as well. The resulting logic smoothly integrates type system and predicate calculus notation and can be viewed as a natural generalization of the notation for constraints arising in role analysis and similar shape analysis approaches.Comment: 30 pages. A version appears in SAS 200
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