Semiconductor optical amplifiers: performance and applications in optical packet switching [Invited]

Semiconductor optical amplifiers (SOAs) are a versatile core technology and the basis for the implementation of a number of key functionalities central to the evolution of highly wavelength-agile all-optical networks. We present an overview of the state of the art of SOAs and summarize a range of applications such as power boosters, preamplifiers, optical linear (gain-clamped) amplifiers, optical gates, and modules based on the hybrid integration of SOAs to yield high-level functionalities such as all-optical wavelength converters/regenerators and small space switching matrices. Their use in a number of proposed optical packet switching situations is also highlighted

Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology

This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW

An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

Programming multi-level quantum gates in disordered computing reservoirs via machine learning and TensorFlow

Novel machine learning computational tools open new perspectives for quantum information systems. Here we adopt the open-source programming library TensorFlow to design multi-level quantum gates including a computing reservoir represented by a random unitary matrix. In optics, the reservoir is a disordered medium or a multi-modal fiber. We show that trainable operators at the input and the readout enable one to realize multi-level gates. We study various qudit gates, including the scaling properties of the algorithms with the size of the reservoir. Despite an initial low slop learning stage, TensorFlow turns out to be an extremely versatile resource for designing gates with complex media, including different models that use spatial light modulators with quantized modulation levels.Comment: Added a new section and a new figure about implementation of the gates by a single spatial light modulator. 9 pages and 4 figure

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator