789 research outputs found
PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning
Floorplanning is the first stage of VLSI physical design. An effective
floorplanning engine definitely has positive impact on chip design speed,
quality and performance. In this paper, we present a novel mathematical model
to characterize non-overlapping of modules, and propose a flat fixed-outline
floorplanning algorithm based on the VLSI global placement approach using
Poisson's equation. The algorithm consists of global floorplanning and
legalization phases. In global floorplanning, we redefine the potential energy
of each module based on the novel mathematical model for characterizing
non-overlapping of modules and an analytical solution of Poisson's equation. In
this scheme, the widths of soft modules appear as variables in the energy
function and can be optimized. Moreover, we design a fast approximate
computation scheme for partial derivatives of the potential energy. In
legalization, based on the defined horizontal and vertical constraint graphs,
we eliminate overlaps between modules remained after global floorplanning, by
modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and
ami49\_x benchmarks show that, our algorithm improves the average wirelength by
at least 2\% and 5\% on small and large scale benchmarks with certain
whitespace, respectively, compared to state-of-the-art floorplanners
Recent Advances in Graph Partitioning
We survey recent trends in practical algorithms for balanced graph
partitioning together with applications and future research directions
3D IC optimal layout design. A parallel and distributed topological approach
The task of 3D ICs layout design involves the assembly of millions of
components taking into account many different requirements and constraints such
as topological, wiring or manufacturability ones. It is a NP-hard problem that
requires new non-deterministic and heuristic algorithms. Considering the time
complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is
superior to any other local search method. Nevertheless, it can often miss to
reach a quasi-optimal solution in 3D spaces. The presented approach uses an
original 3D layout graph partitioning heuristics implemented with use of the
extremal optimization method. The goal is to minimize the total wire-length in
the chip. In order to improve the time complexity a parallel and distributed
Java implementation is applied. Inside one Java Virtual Machine separate
optimization algorithms are executed by independent threads. The work may also
be shared among different machines by means of The Java Remote Method
Invocation system.Comment: 26 pages, 9 figure
FPGA adders: performance evaluation and optimal design
Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.published_or_final_versio
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