Electronic and photonic switching in the atm era

Broadband networks require high-capacity switches in order to properly manage large amounts of traffic fluxes. Electronic and photonic technologies are being used to achieve this objective both allowing different multiplexing and switching techniques. Focusing on the asynchronous transfer mode (ATM), the inherent different characteristics of electronics and photonics makes different architectures feasible. In this paper, different switching structures are described, several ATM switching architectures which have been recently implemented are presented and the implementation characteristics discussed. Three diverse points of view are given from the electronic research, the photonic research and the commercial switches. Although all the architectures where successfully tested, they should also follow different market requirements in order to be commercialised. The characteristics are presented and the architectures projected over them to evaluate their commercial capabilities.Peer ReviewedPostprint (published version

Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs

Is there more than one linkage between Social Network and Inequality?

The paper aims to analyse how income inequality affects social networks strength in fourteen European Countries. We introduce some new evidences by using the ECHP for testing the networks-inequality nexus and being able to construct directly inequality indices from the microdata as well their decomposition. In particular, we focus on two main point: firstly, we analyse how total income inequality could be related to social network; secondly, we introduce the "clustered network" definition, by decomposing total income inequality based on the education level. We test the existence of a pluralism linkage between Social Network and Inequality and many results confirm that the linkage is neither unambiguous nor unidirectional. We introduce and stress some important issue. First, we use dierent levels of social network: narrow, wide and anonymous; second, we use different inequality indexes (different sensitiveness to changes at different part of the income distribution); third, the ambiguous linkage could be explained on one hand by the positive role of emulation and reciprocity behaviors and on the other hand by negative ones of the envy, amoral familism and keeping up with the Joneses mechanisms. Finally, we stress the different roles of within and between components of inequality. Our idea is that higher income inequality - related to the changing education premia - could affect social network formation among individuals through two different channels: higher inequality among dierent educated ind ividuals could raise (clustered networks), while higher inequality among similars could halt the social networks.Social Network ; Inequality ; Clustered Network ; Envy ; Emulation

A schema for generic process tomography sensors

A schema is introduced that aims to facilitate the widespread exploitation of the science of process tomography (PT) that promises a unique multidimensional sensing opportunity. Although PT has been developed to an advanced state, applications have been laboratory or pilot-plant based, configured on an end-to-end basis, and limited typically to the formation of images that attempt to represent process contents. The schema facilitates the fusion of multidimensional internal process state data in terms of a model that yields directly usable process information, either for design model confirmation or for effective plant monitoring or control, here termed a reality visualization model (RVM). A generic view leads to a taxonomy of process types and their respective RVM. An illustrative example is included and a review of typical sensor system components is given

A Carrierless Amplitude Phase (CAP) Modulation Format: Perspective and Prospect in Optical Transmission System

The explosive demand of broadband services nowadays requires data communication systems to have intensive capacity which subsequently increases the need for higher data rate as well. Although implementation of multiple wavelengths channels can be used (e.g. 4 × 25.8 Gb/s for 100 Gb/s connection) for such desired system, it usually leads to cost increment issue which is caused by employment of multiple optical components. Therefore, implementation of advanced modulation format using a single wavelength channel has become a preference to increase spectral efficiency by increasing the data rate for a given transmission system bandwidth. Conventional advanced modulation format however, involves a degree of complexity and costly transmission system. Hence, carrierless amplitude phase (CAP) modulation format has emerged as a promising advanced modulation format candidate due to spectral efficiency improvement ability with reduction of optical transceiver complexity and cost. The intriguing properties of CAP modulation format are reviewed as an attractive prospect in optical transmission system applications

From MARTE to Reconfigurable NoCs: A model driven design methodology

Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this paper, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

A Modeling Approach based on UML/MARTE for GPU Architecture

Nowadays, the High Performance Computing is part of the context of embedded systems. Graphics Processing Units (GPUs) are more and more used in acceleration of the most part of algorithms and applications. Over the past years, not many efforts have been done to describe abstractions of applications in relation to their target architectures. Thus, when developers need to associate applications and GPUs, for example, they find difficulty and prefer using API for these architectures. This paper presents a metamodel extension for MARTE profile and a model for GPU architectures. The main goal is to specify the task and data allocation in the memory hierarchy of these architectures. The results show that this approach will help to generate code for GPUs based on model transformations using Model Driven Engineering (MDE).Comment: Symposium en Architectures nouvelles de machines (SympA'14) (2011