117 research outputs found

    On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

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    This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

    GNSS-SDR pseudorange quality and single point positioning performance assessment

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    In recent years, we have witnessed a growing demand for GNSS receiver customization in terms of modification of signal acquisition, tracking, and processing strategies. Such demands may be addressed by software-defined receivers (SDRs) which refers to an ensemble of hardware and software technologies and allows re-configurable radio communication architectures. The crux of the SDRs is the replacement of the hardware components through software modules. In this paper, we assess the quality of GNSS observables acquired by SDR against the selected u-blox low-cost receiver. In the following, we investigate the performance level of single point positioning that may be reached with an ultra-low-cost SDR and compare it to that of the low-cost GNSS receiver. The signal quality assessment revealed a comparable performance in terms of carrier-to-noise density ratio and a significant out-performance of the u-blox over SDR in terms of code pseudorange noise. The experimentation in the positioning domain proved that software-defined receivers may offer a position solution with three-dimensional standard deviation error at the level of 5.2 m in a single point positioning mode that is noticeably poorer accuracy as compared to the low-cost receiver. Such results demonstrate that there is still room for SDR positioning accuracy improvement

    Reconfigurable Antenna Systems: Platform implementation and low-power matters

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    Antennas are a necessary and often critical component of all wireless systems, of which they share the ever-increasing complexity and the challenges of present and emerging trends. 5G, massive low-orbit satellite architectures (e.g. OneWeb), industry 4.0, Internet of Things (IoT), satcom on-the-move, Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles, all call for highly flexible systems, and antenna reconfigurability is an enabling part of these advances. The terminal segment is particularly crucial in this sense, encompassing both very compact antennas or low-profile antennas, all with various adaptability/reconfigurability requirements. This thesis work has dealt with hardware implementation issues of Radio Frequency (RF) antenna reconfigurability, and in particular with low-power General Purpose Platforms (GPP); the work has encompassed Software Defined Radio (SDR) implementation, as well as embedded low-power platforms (in particular on STM32 Nucleo family of micro-controller). The hardware-software platform work has been complemented with design and fabrication of reconfigurable antennas in standard technology, and the resulting systems tested. The selected antenna technology was antenna array with continuously steerable beam, controlled by voltage-driven phase shifting circuits. Applications included notably Wireless Sensor Network (WSN) deployed in the Italian scientific mission in Antarctica, in a traffic-monitoring case study (EU H2020 project), and into an innovative Global Navigation Satellite Systems (GNSS) antenna concept (patent application submitted). The SDR implementation focused on a low-cost and low-power Software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. In a second embodiment, the flexibility of the SDR paradigm has been traded off to avoid the power consumption associated to the relevant operating system. Application field of reconfigurable antenna is, however, not limited to a better management of the energy consumption. The analysis has also been extended to satellites positioning application. A novel beamforming method has presented demonstrating improvements in the quality of signals received from satellites. Regarding those who deal with positioning algorithms, this advancement help improving precision on the estimated position

    FPGA-Based Software GNSS Receiver Design for Satellite Applications

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    Global Navigation Satellite System (GNSS) receiver technology has tremendous scope for satellite applications such as radio occultation, precise orbit determination and reflectometry. Spaceborne GNSS receivers are characterised by low power requirements, high processing speed and radiation resistant electronic components. Such sophisticated receivers, also called hardware GNSS receivers, are fabricated for specific applications and hence lack design flexibility. On the other hand, a software GNSS receiver allows easy design modifications without any hardware component replacement. Software receivers employ reconfigurable hardware elements called Field Programmable Gate Arrays (FPGAs). In this research, a low-power, low-cost software GNSS receiver has been designed and developed using a combination of a microprocessor and FPGA (System-on-Chip or SoC). The developed software GNSS receiver is capable of detecting GPS satellites, tracking them and computing receiver position estimates. Efficient task partitioning is achieved by implementing operations in both, the FPGA and the microprocessor. Also demonstrated is the improvement of processing speed by 20% when certain GNSS receiver operations are performed in the FPGA instead of the microprocessor

    A scalable real-time processing chain for radar exploiting illuminators of opportunity

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    Includes bibliographical references.This thesis details the design of a processing chain and system software for a commensal radar system, that is, a radar that makes use of illuminators of opportunity to provide the transmitted waveform. The stages of data acquisition from receiver back-end, direct path interference and clutter suppression, range/Doppler processing and target detection are described and targeted to general purpose commercial off-the-shelf computing hardware. A detailed low level design of such a processing chain for commensal radar which includes both processing stages and processing stage interactions has, to date, not been presented in the Literature. Furthermore, a novel deployment configuration for a networked multi-site FM broadcast band commensal radar system is presented in which the reference and surveillance channels are record at separate locations
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