MODELING AND SIMULATION OF A SEMICONDUCTOR MANUFACTURING FAB FOR CYCLE TIME ANALYSIS

The goal of the thesis is to conduct a study of the effects of scheduling policies and machine failures on the manufacturing cycle time of the Integrated Circuit (IC) manufacturing process for two processor chips, namely Skylake and Kabylake, manufactured by Intel. The fab simulation model was developed as First in First Out (FIFO), Shortest Processing Time (SPT), Priority based (PB), and Failure FIFO (machine failures) model, and the average cycle times and queue waiting times under the four scheduling policy models were compared for both the Skylake and Kabylake wafers. The study revealed that scheduling policies SPT and PB increased the average cycle time for Skylake wafers while decreasing the average cycle time for the Kabylake wafers, when compared to the base FIFO model. Machine failures increased the average cycle time for both types of wafers

Practical Extensions to Cycle Time Approximations for the G=G=m-Queue With Applications

Abstract-Approximate closed form expressions for the mean cycle time in a -queue often serve as practical and intuitive alternatives to more exact but less tractable analyses. However, the -queue model may not fully address issues that arise in practical manufacturing systems. Such issues include tools with production parallelism, tools that are idle with work in process, travel to the queue, and the tendency of lots to defect from a failed server and return to the queue even after they have entered production. In this paper, we extend popular approximate mean cycle time formulae to address these practical manufacturing issues. Employing automated data extraction algorithms embedded in software, we test the approximations using parameters gleaned from production tool groups in IBM's 200 mm semiconductor wafer fabricator. Note to Practitioners-We develop extensions to intuitive closed-form approximations for the mean cycle time in queueing networks. Such approximations can be used to analyze the tradeoffs between equipment utilization and cycle time in a manufacturing facility. The extensions incorporate issues of practical import that have not been modeled in the literature and were motivated by the inability of existing models to accurately describe the performance of manufacturing in IBM's 200 mm semiconductor wafer fabricator. The utility of our extensions is that, using automated data collection systems, we are able to well model production tools and elucidate the sources of cycle time. Index Terms-Production management, queueing analysis, semiconductor device manufacture

Machine Learning in Manufacturing towards Industry 4.0: From ‘For Now’ to ‘Four-Know’

While attracting increasing research attention in science and technology, Machine Learning (ML) is playing a critical role in the digitalization of manufacturing operations towards Industry 4.0. Recently, ML has been applied in several fields of production engineering to solve a variety of tasks with different levels of complexity and performance. However, in spite of the enormous number of ML use cases, there is no guidance or standard for developing ML solutions from ideation to deployment. This paper aims to address this problem by proposing an ML application roadmap for the manufacturing industry based on the state-of-the-art published research on the topic. First, this paper presents two dimensions for formulating ML tasks, namely, ’Four-Know’ (Know-what, Know-why, Know-when, Know-how) and ’Four-Level’ (Product, Process, Machine, System). These are used to analyze ML development trends in manufacturing. Then, the paper provides an implementation pipeline starting from the very early stages of ML solution development and summarizes the available ML methods, including supervised learning methods, semi-supervised methods, unsupervised methods, and reinforcement methods, along with their typical applications. Finally, the paper discusses the current challenges during ML applications and provides an outline of possible directions for future developments

Smart Feature Selection to enable Advanced Virtual Metrology

The present dissertation enhances the research in computer science, especially state of the art Machine Learning (ML), in the field of process development in Semiconductor Manufacturing (SM) by the invention of a new Feature Selection (FS) algorithm to discover the most important equipment and context parameters for highest performance of predicting process results in a newly developed advanced Virtual Metrology (VM) system. In complex high-mixture-low-volume SM, chips or rather silicon wafers for numerous products and technologies are manufactured on the same equipment. Process stability and control are key factors for the production of highest quality semiconductors. Advanced Process Control (APC) monitors manufacturing equipment and intervenes in the equipment control if critical states occur. Besides Run-To-Run (R2R) control and Fault Detection and Classification (FDC) new process control development activities focus on VM which predicts metrology results based on productive equipment and context data. More precisely, physical equipment parameters combined with logistical information about the manufactured product are used to predict the process result. The compulsory need for a reliable and most accurate VM system arises to imperatively reduce time and cost expensive physical metrology as well as to increase yield and stability of the manufacturing processes while concurrently minimizing economic expenditures and associated data flow. The four challenges of (1) efficiency of development and deployment of a corporate-wide VM system, (2) scalability of enterprise data storage, data traffic and computational effort, (3) knowledge discovery out of available data for future enhancements and process developments as well as (4) highest accuracy including reliability and reproducibility of the prediction results are so far not successfully mastered at the same time by any other approach. Many ML techniques have already been investigated to build prediction models based on historical data. The outcomes are only partially satisfying in order to achieve the ambitious objectives in terms of highest accuracy resulting in tight control limits which tolerate almost no deviation from the intended process result. For optimization of prediction performance state of the art process engineering requirements lead to three criteria for assessment of the ML algorithm for the VM: outlier detection, model robustness with respect to equipment degradation over time and ever-changing manufacturing processes adapted for further development of products and technologies and finally highest prediction accuracy. It has been shown that simple regression methods fail in terms of prediction accuracy, outlier detection and model robustness while higher-sophisticated regression methods are almost able to constantly achieve these goals. Due to quite similar but still not optimal prediction performance as well as limited computational feasibility in case of numerous input parameters, the choice of superior ML regression methods does not ultimately resolve the problem. Considering the entire cycle of Knowledge Discovery in Databases including Data Mining (DM) another task appears to be crucial: FS. An optimal selection of the decisive parameters and hence reduction of the input space dimension boosts the model performance by omitting redundant as well as spurious information. Various FS algorithms exist to deal with correlated and noisy features, but each of its own is not capable to ensure that the ambitious targets for VM can be achieved in prevalent high-mixture-low-volume SM. The objective of the present doctoral thesis is the development of a smart FS algorithm to enable a by this advanced and also newly developed VM system to comply with all imperative requirements for improved process stability and control. At first, a new Evolutionary Repetitive Backward Elimination (ERBE) FS algorithm is implemented combining the advantages of a Genetic Algorithm (GA) with Leave-One-Out (LOO) Backward Elimination as wrapper for Support Vector Regression (SVR). At second, a new high performance VM system is realized in the productive environment of High Density Plasma (HDP) Chemical Vapor Deposition (CVD) at the Infineon frontend manufacturing site Regensburg. The advanced VM system performs predictions based on three state of the art ML methods (i.e. Neural Network (NN), Decision Tree M5’ (M5’) & SVR) and can be deployed on many other process areas due to its generic approach and the adaptive design of the ERBE FS algorithm. The developed ERBE algorithm for smart FS enhances the new advanced VM system by revealing evidentially the crucial features for multivariate nonlinear regression. Enabling most capable VM turns statistical sampling metrology with typically 10% coverage of process results into a 100% metrological process monitoring and control. Hence, misprocessed wafers can be detected instantly. Subsequent rework or earliest scrap of those wafers result in significantly increased stability of subsequent process steps and thus higher yield. An additional remarkable benefit is the reduction of production cycle time due to the possible saving of time consuming physical metrology resulting in an increase of production volume output up to 10% in case of fab-wide implementation of the new VM system

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

Analytics and Intelligence for Smart Manufacturing

Digital transformation is one of the main aspects emerged by the current 4.0 revolution. It embraces the integration between the digital and physical environment,including the application of modelling and simulation techniques, visualization, and data analytics in order to manage the overall product life cycle

Proceedings of the Scientific-Practical Conference "Research and Development - 2016"

talent management; sensor arrays; automatic speech recognition; dry separation technology; oil production; oil waste; laser technolog

Sustainable Smart Cities and Smart Villages Research

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [There is ever more research on smart cities and new interdisciplinary approaches proposed on the study of smart cities. At the same time, problems pertinent to communities inhabiting rural areas are being addressed, as part of discussions in contigious fields of research, be it environmental studies, sociology, or agriculture. Even if rural areas and countryside communities have previously been a subject of concern for robust policy frameworks, such as the European Union’s Cohesion Policy and Common Agricultural Policy Arguably, the concept of ‘the village’ has been largely absent in the debate. As a result, when advances in sophisticated information and communication technology (ICT) led to the emergence of a rich body of research on smart cities, the application and usability of ICT in the context of a village has remained underdiscussed in the literature. Against this backdrop, this volume delivers on four objectives. It delineates the conceptual boundaries of the concept of ‘smart village’. It highlights in which ways ‘smart village’ is distinct from ‘smart city’. It examines in which ways smart cities research can enrich smart villages research. It sheds light on the smart village research agenda as it unfolds in European and global contexts.

Proceedings of the 2nd Conference on Production Systems and Logistics (CPSL 2021)

Proceedings of the CPSL 202