83,687 research outputs found

    Power efficient job scheduling by predicting the impact of processor manufacturing variability

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    Modern CPUs suffer from performance and power consumption variability due to the manufacturing process. As a result, systems that do not consider such variability caused by manufacturing issues lead to performance degradations and wasted power. In order to avoid such negative impact, users and system administrators must actively counteract any manufacturing variability. In this work we show that parallel systems benefit from taking into account the consequences of manufacturing variability when making scheduling decisions at the job scheduler level. We also show that it is possible to predict the impact of this variability on specific applications by using variability-aware power prediction models. Based on these power models, we propose two job scheduling policies that consider the effects of manufacturing variability for each application and that ensure that power consumption stays under a system-wide power budget. We evaluate our policies under different power budgets and traffic scenarios, consisting of both single- and multi-node parallel applications, utilizing up to 4096 cores in total. We demonstrate that they decrease job turnaround time, compared to contemporary scheduling policies used on production clusters, up to 31% while saving up to 5.5% energy.Postprint (author's final draft

    Multi-threaded Simulation of 4G Cellular Systems within the LTE-Sim Framework

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    Nowadays, an always increasing number of researchers and industries are putting a large effort in the design and the implementation of protocols, algorithms, and network architectures targeted at the the emerging 4G cellular technology. In this context, multi-core/multi-processor simulation tools can accelerate their activities by drastically reducing the time required to simulate complex scenarios. Unfortunately, today's available tools are mostly single-threaded and they cannot exploit the performance gain offered by parallel programming approaches. To bridge this gap, we have significantly upgraded the LTE-Sim framework by implementing a concurrent scheduling algorithm, namely the Multi-Master Scheduler, aimed at efficiently handling events in a parallel manner, while guaranteeing the correct execution of the simulation itself. Experimental results will demonstrate the effectiveness of our proposal and the performance gain that can be achieved with respect to other classical event scheduling algorithms

    Analysis of packet scheduling for UMTS EUL - design decisions and performance evaluation

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    The UMTS Enhanced Uplink (EUL) provides higher capacity, increased data rates and smaller latency on the communication link from users towards the network. In this paper we present a performance comparison of three distinct EUL scheduling schemes (one-by-one, partial parallel and full parallel) taking into account both the packet level characteristics and the flow level dynamics due to the (random) user behaviour.\ud Using a very efficient hybrid analytical and simulation approach we analyse the three schemes with respect to performance measures such as mean file transfer time and fairness. In UMTS, a significant part of the system capacity will be used to support non-elastic voice traffic. Hence, part of our investigation is dedicated to the effects that the volume of voice traffic has on the performance of the elastic traffic supported by the EUL. Finally, we evaluate the impact that implementation specifics of a full parallel scheduler has on these measures.\ud \ud Our main conclusion is that our partial parallel scheduler, which is a hybrid between the one-by-one and full parallel, outperforms the other two schedulers in terms of mean flow transfer time, and is less sensitive to volume and nature of voice traffic. However, under certain circumstances, the partial parallel scheduler exhibits a somewhat lower fairness than the alternatives
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