Survey of partitioning techniques in silicon compilation

In the silicon compilation design process, partitioning is usually the first problem to be investigated because partitioning algorithms form the backbone of many algorithms including: system synthesis, processor synthesis, floorplanning, and placement. In this survey, several partitioning techniques will be examined. In addition, this paper will review the partitioning algorithms used by synthesis systems at different design levels

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

A flexible design framework for autonomous mowing

Thesis (S.M. in Engineering and Management)--Massachusetts Institute of Technology, Engineering Systems Division, System Design and Management Program, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 93-95).This work outlines the creation of a flexible design framework for autonomous mowing to meet changing customer needs and functionality across a spectrum of applications from residential areas to sport complexes. The thesis has the objective of creating an optimized architecture to meet a range of functionality that delivers value in diverse customer mission segments. Additionally, autonomous mowing is supported by fast moving technology domains that create the need for technology selection strategies that anticipate future trends in critical metrics. Currently an early dominant design has been produced, but increasing competition is actively advancing the current state of the art for autonomous mowing. An analysis to determine where the value lies in the system, much like the evolution of the PC, determines when to shift between modular and integrated designs. As designs become modular and flexible the importance of knowing which areas of the system capture value and lead to revenue is critical for a company's continued success in the domain. Using this framework Pareto frontiers were developed using genetic algorithms that clearly show the sensitivity between manufacturing costs and total life cycle cost to the consumer using 970 generations. A platform architecture analysis provided a 9% increase in a portfolio Net Present Value by determining an optimum commonality and differentiation plan over that of individually optimized customer segment offerings. This analysis also determines if an open source approach to innovation is viable for increased customer satisfaction while supporting increased manufacturer revenues (Hippel, 2005).by Justin Kraft.S.M.in Engineering and Managemen

Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-programmable Gate Arrays

Many space applications, such as vision-based systems, synthetic aperture radar, and radar altimetry rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the tradition in DSP processing has been to use fixed point number representation, only recently have DSP processors begun to incorporate floating point arithmetic units, even though most of these units handle only single precision floating point addition/subtraction, multiplication, and occasionally division. While DSP processors are slowly evolving to meet the numerical requirements of newer space applications, FPGA densities have rapidly increased to parallel and surpass even the gate densities of many DSP processors and commodity CPUs. This makes them attractive platforms to implement compute-intensive DSP computations. Even in the presence of this clear advantage on the side of FPGAs, few attempts have been made to examine how wide precision floating point arithmetic, particularly division and square root operations, can perform on FPGAs to support these compute-intensive DSP applications. In this context, this thesis presents the sequential and pipelined designs of IEEE-754 compliant double floating point division and square root operations based on low radix digit recurrence algorithms. FPGA implementations of these algorithms have the advantage of being easily testable. In particular, the pipelined designs are synthesized based on careful partial and full unrolling of the iterations in the digit recurrence algorithms. In the overall, the implementations of the sequential and pipelined designs are common-denominator implementations which do not use any performance-enhancing embedded components such as multipliers and block memory. As these implementations exploit exclusively the fine-grain reconfigurable resources of Virtex FPGAs, they are easily portable to other FPGAs with similar reconfigurable fabrics without any major modifications. The pipelined designs of these two operations are evaluated in terms of area, throughput, and dynamic power consumption as a function of pipeline depth. Pipelining experiments reveal that the area overhead tends to remain constant regardless of the degree of pipelining to which the design is submitted, while the throughput increases with pipeline depth. In addition, these experiments reveal that pipelining reduces power considerably in shallow pipelines. Pipelining further these designs does not necessarily lead to significant power reduction. By partitioning these designs into deeper pipelines, these designs can reach throughputs close to the 100 MFLOPS mark by consuming a modest 1% to 8% of the reconfigurable fabric within a Virtex-II XC2VX000 (e.g., XC2V1000 or XC2V6000) FPGA

Conference on Intelligent Robotics in Field, Factory, Service, and Space (CIRFFSS 1994), volume 1

The AIAA/NASA Conference on Intelligent Robotics in Field, Factory, Service, and Space (CIRFFSS '94) was originally proposed because of the strong belief that America's problems of global economic competitiveness and job creation and preservation can partly be solved by the use of intelligent robotics, which are also required for human space exploration missions. Individual sessions addressed nuclear industry, agile manufacturing, security/building monitoring, on-orbit applications, vision and sensing technologies, situated control and low-level control, robotic systems architecture, environmental restoration and waste management, robotic remanufacturing, and healthcare applications

State of the art survey of technologies applicable to NASA's aeronautics, avionics and controls program

The state of the art survey (SOAS) covers six technology areas including flightpath management, aircraft control system, crew station technology, interface & integration technology, military technology, and fundamental technology. The SOAS included contributions from over 70 individuals in industry, government, and the universities

Assessment of avionics technology in European aerospace organizations

This report provides a summary of the observations and recommendations made by a technical panel formed by the National Aeronautics and Space Administration (NASA). The panel, comprising prominent experts in the avionics field, was tasked to visit various organizations in Europe to assess the level of technology planned for use in manufactured civil avionics in the future. The primary purpose of the study was to assess avionics systems planned for implementation or already employed on civil aircraft and to evaluate future research, development, and engineering (RD&E) programs, address avionic systems and aircraft programs. The ultimate goal is to ensure that the technology addressed by NASa programs is commensurate with the needs of the aerospace industry at an international level. The panel focused on specific technologies, including guidance and control systems, advanced cockpit displays, sensors and data networks, and fly-by-wire/fly-by-light systems. However, discussions the panel had with the European organizations were not limited to these topics

Internet of Things. Information Processing in an Increasingly Connected World

This open access book constitutes the refereed post-conference proceedings of the First IFIP International Cross-Domain Conference on Internet of Things, IFIPIoT 2018, held at the 24th IFIP World Computer Congress, WCC 2018, in Poznan, Poland, in September 2018. The 12 full papers presented were carefully reviewed and selected from 24 submissions. Also included in this volume are 4 WCC 2018 plenary contributions, an invited talk and a position paper from the IFIP domain committee on IoT. The papers cover a wide range of topics from a technology to a business perspective and include among others hardware, software and management aspects, process innovation, privacy, power consumption, architecture, applications

Aeronautical Engineering: A continuing bibliography (supplement 158)

This bibliography lists 499 reports, articles and other documents introduced into the NASA scientific and technical information system in January 1983