Advanced physical modeling of SiOx resistive random access memories

We apply a three-dimensional (3D) physical simulator, coupling self-consistently stochastic kinetic Monte Carlo descriptions of ion and electron transport, to investigate switching in silicon-rich silica (SiOx) redox-based resistive random-access memory (RRAM) devices. We explain the intrinsic nature of resistance switching of the SiOx layer, and demonstrate the impact of self-heating effects and the initial vacancy distributions on switching. We also highlight the necessity of using 3D physical modelling to predict correctly the switching behavior. The simulation framework is useful for exploring the little-known physics of SiOx RRAMs and RRAM devices in general. This proves useful in achieving efficient device and circuit designs, in terms of performance, variability and reliability

Investigation of resistance switching in SiOx RRAM cells using a 3D multi-scale kinetic Monte Carlo simulator

We employ an advanced three-dimensional (3D) electro-thermal simulator to explore the physics and potential of oxide-based resistive random-access memory (RRAM) cells. The physical simulation model has been developed recently, and couples a kinetic Monte Carlo study of electron and ionic transport to the self-heating phenomenon while accounting carefully for the physics of vacancy generation and recombination, and trapping mechanisms. The simulation framework successfully captures resistance switching, including the electroforming, set and reset processes, by modeling the dynamics of conductive filaments in the 3D space. This work focuses on the promising yet less studied RRAM structures based on silicon-rich silica (SiOx) RRAMs. We explain the intrinsic nature of resistance switching of the SiOx layer, analyze the effect of self-heating on device performance, highlight the role of the initial vacancy distributions acting as precursors for switching, and also stress the importance of using 3D physics-based models to capture accurately the switching processes. The simulation work is backed by experimental studies. The simulator is useful for improving our understanding of the little-known physics of SiOx resistive memory devices, as well as other oxide-based RRAM systems (e.g. transition metal oxide RRAMs), offering design and optimization capabilities with regard to the reliability and variability of memory cells

Reconfigurable three-terminal logic devices using phase-change materials

Conventional solid-state and mass storage memories (such as SRAM, DRAM and the hard disk drive HDD) are facing many technological challenges to meet the ever-increasing demand for fast, low power and cheap data storage solutions. This is compounded by the current conventional computer architectures (such as the von Neumann architecture) with separate processing and storage functionalities and hence data transfer bottlenecks and increased silicon footprint. Beyond the von Neumann computer architecture, the combination of arithmetic-logic processing and (collocally) storage circuits provide a new and promising alternative for computer systems that overcome the many limitations of current technology. However, there are many technical challenges that face the implementation of universal blocks of both logic and memory functions using conventional silicon technology (transistor-transistor logic - TTL, and complementary metal oxide semiconductors - CMOS). Phase-change materials, such as Ge2Sb2Te5 (GST), provide a potential complement or replacement to these technologies to provide both processing and, collocally, storage capability. Existing research in phase-change memory technologies focused on two-terminal non-volatile devices for different memory and logic applications due to their ability to achieve logic-resistive switching in nanosecond time scale, their scalability down to few nanometer-scale cells, and low power requirements. To perform logic functionality, current two-terminal phase-change logic devices need to be connected in series or parallel circuits, and require sequential inputs to perform the required logic function (such as NAND and NOR). In this research programme, three-terminal (3T) non-volatile phase-change memories are proposed and investigated as potential alternative logic cells with simultaneous inputs as reconfigurable, non-volatile logic devices. A vertical 3T logic device structure is proposed in this work based on existing phase-change based memory cell architecture and original concept work by Ovshinsky. A comprehensive, multi-physics finite-element model of the vertical 3T device was constructed in Comsol Multiphysics. This model solves Laplace's equation for the electric potential due to the application of voltage sources. The calculated electric potential and fields provide the Joule heating source in the device, which is used to compute the temperature distribution through solution of the heat diffusion equation, which is necessary to activate the thermally-driven phase transition process. The physically realistic and computationally efficient nucleation- growth model was numerically implemented to model the phase change and resistance change in the Ge2Sb2Te5 (GST) phase-change material in the device, which is combined with the finite- element model using the Matlab programming interface. The changes in electrical and thermal conductivities in the GST region are taken into account following the thermally activated phase transformations between the amorphous-crystalline states using effective medium theory. To determine the appropriate voltage and temperature conditions for the SET and RESET operations, and to optimise the materials and thicknesses of the thermal and heating layers in the device, comprehensive steady-state parametric simulations were carried out using the finite-element multi-physics model. Simulations of transient cycles of writing (SET) and erasing (RESET) processes using appropriate voltage pulses were then carried out on the designed vertical 3T device to study the phase transformations for practical reconfigurable logic operations. The simulations indicated excellent resistance contrast between the logic 1 and 0 states, and successfully demonstrated the feasibility of programming the logic functions of NAND and NOR gates using this 3T configuration

Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

Nanoscale Carbon-Based Memory Devices

Amorphous carbon-based memories have gained traction in recent years due to their good scalability and switching performance and are an important contender to close the performance gap between fast but volatile DRAM and slow but non-volatile flash memory. A writing and erasing process driven by the electrically induced formation and rupture of a conductive filament permits switching times in the range of a few nanoseconds. Further, the memristive property of amorphous carbon allows the implementation of beyond von Neumann computation paradigms. However, ‘pure’ amorphous memories have a low cyclic endurance. To overcome this and to exploit beyond von Neumann computation, devices based on oxygenated amorphous carbon were employed here. The first part of this thesis evaluated the switching performance and data retention capabilities of tetrahedral amorphous carbon memories. Switching times below 10 ns were achieved for the SET as well as for the RESET times. An energy consumption below 1 pJ was obtained, while data could be retained for more than 300 s at 450 °C. Further, evidence was provided that the SET process is not induced by an electric field alone. A finite-element simulation was employed in the second part of this thesis to reproduce the experimentally determined conductivity of tetrahedral amorphous carbon (ta-C) memory devices and to shine light on the conditions at the onset switching from the high to low resistance states (dielectric breakdown). The maximum temperature observed at dielectric breakdown was 1615 K. It was found that a reduction of the lateral cell radius from 25 nm to 15 nm and 10 nm increases the switching performance by reducing the switching current from 34 µA to 20 µA and 8 µA. The third part of this thesis evaluated the switching performance, temperature stability, multilevel storage and memcomputing capabilities of oxygenated amorphous carbon. Switching times below 10 ns for both, SET and RESET were demonstrated. A 3-level (1 1 /2 bits) data storage was achieved using three different resistance states. Further, a memcomputing approach was implemented using a base-16 accumulation response with energy consumptions as low as <100 fJ per pulse. Additionally, a finite element simulation of a device in the low resistance state (LRS) was used to illustrate the correlation between device resistance and Joule heating effects

A Superconducting Nanowire-based Architecture for Neuromorphic Computing

Neuromorphic computing is poised to further the success of software-based neural networks by utilizing improved customized hardware. However, the translation of neuromorphic algorithms to hardware specifications is a problem that has been seldom explored. Building superconducting neuromorphic systems requires extensive expertise in both superconducting physics and theoretical neuroscience. In this work, we aim to bridge this gap by presenting a tool and methodology to translate algorithmic parameters into circuit specifications. We first show the correspondence between theoretical neuroscience models and the dynamics of our circuit topologies. We then apply this tool to solve linear systems by implementing a spiking neural network with our superconducting nanowire-based hardware.Comment: 29 pages, 10 figure

SUSTAINABLE ENERGY HARVESTING TECHNOLOGIES – PAST, PRESENT AND FUTURE

Chapter 8: Energy Harvesting Technologies: Thick-Film Piezoelectric Microgenerato