To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques

Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1][10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed. DOI: 10.17762/ijritcc2321-8169.150314

Advanced digital SAR processing study

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented

Design and implementation of a modular controller for robotic machines

This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design incorporates novel communication, hardware, and software architectures. This was motivated by current industrial needs for distributed control systems due to growing demand for less complexity, more processing power, flexibility, and greater fault tolerance. To this end, three main contributions were made. Most distributed control architectures depend on multi-tier heterogeneous communication networks requiring linking devices and/or complex middleware. In this study, first, a communication architecture was proposed and implemented with a homogenous network employing the ubiquitous Ethernet for both real-time and non real-time communication. This was achieved by a producer-consumer coordination model for real-time data communication over a segmented network, and a client-server model for point-to-point transactions. The protocols deployed use a Time-Triggered (TT) approach to schedule real-time tasks on the network. Unlike other TT approaches, the scheduling mechanism does not need to be configured explicitly when controller nodes are added or removed. An implicit clock synchronization technique was also developed to complement the architecture. Second, a reconfigurable mechanism based on an auto-configuration protocol was developed. Modules on the network use this protocol to automatically detect themselves, establish communication, and negotiate for a desired configuration. Third, the research demonstrated hardware/software co-design as a contribution to the growing discipline of mechatronics. The IMC consists of a motion controller board designed and prototyped in-house, and a Java microcontroller. An IMC is mapped to each machine/robot axis, and an additional IMC can be configured to serve as a real-time coordinator. The entire architecture was implemented in Java, thus reinforcing uniformity, simplicity, modularity, and openness. Evaluation results showed the potential of the flexible controller to meet medium to high performance machining requirements

Spaceborne memory organization, phase 1 Final report

Application of associative memories to data processing for future space vehicle

차세대 HBM 용 고집적, 저전력 송수신기 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 정덕균.This thesis presents design techniques for high-density power-efficient transceiver for the next-generation high bandwidth memory (HBM). Unlike the other memory interfaces, HBM uses a 3D-stacked package using through-silicon via (TSV) and a silicon interposer. The transceiver for HBM should be able to solve the problems caused by the 3D-stacked package and TSV. At first, a data (DQ) receiver for HBM with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift is proposed. The self-tracking loop achieves low power and small area by uti-lizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage differ-ence and detects the phase skew from the voltage difference. An offset calibra-tion scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing cir-cuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver op-erates without any performance degradation under a ± 10% supply variation. In a second prototype IC, a high-density transceiver for HBM with a feed-forward-equalizer (FFE)-combined crosstalk (XT) cancellation scheme is pre-sented. To compensate for the XT, the transmitter pre-distorts the amplitude of the FFE output according to the XT. Since the proposed XT cancellation (XTC) scheme reuses the FFE implemented to equalize the channel loss, additional circuits for the XTC is minimized. Thanks to the XTC scheme, a channel pitch can be significantly reduced, allowing for the high channel density. Moreover, the 3D-staggered channel structure removes the ground layer between the verti-cally adjacent channels, which further reduces a cross-sectional area of the channel per lane. The test chip including 6 data lanes is fabricated in 65 nm CMOS technology. The 6-mm channels are implemented on chip to emulate the silicon interposer between the HBM and the processor. The operation of the XTC scheme is verified by simultaneously transmitting 4-Gb/s data to the 6 consecutive channels with 0.5-um pitch and the XTC scheme reduces the XT-induced jitter up to 78 %. The measurement result shows that the transceiver achieves the throughput of 8 Gb/s/um. The transceiver occupies 0.05 mm2 for 6 lanes and consumes 36.6 mW at 6 x 4 Gb/s.본 논문에서는 차세대 HBM을 위한 고집적 저전력 송수신기 설계 방법을 제안한다. 첫 번째로, 전압 및 온도 변화에 의한 데이터와 클럭 간 위상 차이를 보상할 수 있는 자체 추적 루프를 가진 데이터 수신기를 제안한다. 제안하는 자체 추적 루프는 데이터 전송 속도와 같은 속도로 동작하는 위상 검출기를 사용하여 전력 소모와 면적을 줄였다. 또한 메모리의 쓰기 훈련 (write training) 과정을 이용하여 효과적으로 위상 검출기의 오프셋을 보상할 수 있는 방법을 제안한다. 제안하는 데이터 수신기는 65 nm 공정으로 제작되어 4.8 Gb/s에서 370 fJ/b을 소모하였다. 또한 10 % 의 전압 변화에 대하여 안정적으로 동작하는 것을 확인하였다. 두 번째로, 피드 포워드 이퀄라이저와 결합된 크로스 토크 보상 방식을 활용한 고집적 송수신기를 제안한다. 제안하는 송신기는 크로스 토크 크기에 해당하는 만큼 송신기 출력을 왜곡하여 크로스 토크를 보상한다. 제안하는 크로스 토크 보상 방식은 채널 손실을 보상하기 위해 구현된 피드 포워드 이퀄라이저를 재활용함으로써 추가적인 회로를 최소화한다. 제안하는 송수신기는 크로스 토크가 보상 가능하기 때문에, 채널 간격을 크게 줄여 고집적 통신을 구현하였다. 또한 집적도를 더 증가시키기 위해 세로로 인접한 채널 사이의 차폐 층을 제거한 적층 채널 구조를 제안한다. 6개의 송수신기를 포함한 프로토타입 칩은 65 nm 공정으로 제작되었다. HBM과 프로세서 사이의 silicon interposer channel 을 모사하기 위한 6 mm 의 채널이 칩 위에 구현되었다. 제안하는 크로스 토크 보상 방식은 0.5 um 간격의 6개의 인접한 채널에 동시에 데이터를 전송하여 검증되었으며, 크로스 토크로 인한 지터를 최대 78 % 감소시켰다. 제안하는 송수신기는 8 Gb/s/um 의 처리량을 가지며 6 개의 송수신기가 총 36.6 mW의 전력을 소모하였다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUND ON HIGH-BANDWIDTH MEMORY 6 2.1 OVERVIEW 6 2.2 TRANSCEIVER ARCHITECTURE 10 2.3 READ/WRITE OPERATION 15 2.3.1 READ OPERATION 15 2.3.2 WRITE OPERATION 19 CHAPTER 3 BACKGROUNDS ON COUPLED WIRES 21 3.1 GENERALIZED MODEL 21 3.2 EFFECT OF CROSSTALK 26 CHAPTER 4 DQ RECEIVER WITH BAUD-RATE SELF-TRACKING LOOP 29 4.1 OVERVIEW 29 4.2 FEATURES OF DQ RECEIVER FOR HBM 33 4.3 PROPOSED PULSE-TO-CHARGE PHASE DETECTOR 35 4.3.1 OPERATION OF PULSE-TO-CHARGE PHASE DETECTOR 35 4.3.2 OFFSET CALIBRATION 37 4.3.3 OPERATION SEQUENCE 39 4.4 CIRCUIT IMPLEMENTATION 42 4.5 MEASUREMENT RESULT 46 CHAPTER 5 HIGH-DENSITY TRANSCEIVER FOR HBM WITH 3D-STAGGERED CHANNEL AND CROSSTALK CANCELLATION SCHEME 57 5.1 OVERVIEW 57 5.2 PROPOSED 3D-STAGGERED CHANNEL 61 5.2.1 IMPLEMENTATION OF 3D-STAGGERED CHANNEL 61 5.2.2 CHANNEL CHARACTERISTICS AND MODELING 66 5.3 PROPOSED FEED-FORWARD-EQUALIZER-COMBINED CROSSTALK CANCELLATION SCHEME 72 5.4 CIRCUIT IMPLEMENTATION 77 5.4.1 OVERALL ARCHITECTURE 77 5.4.2 TRANSMITTER WITH FFE-COMBINED XTC 79 5.4.3 RECEIVER 81 5.5 MEASUREMENT RESULT 82 CHAPTER 6 CONCLUSION 93 BIBLIOGRAPHY 95 초 록 102Docto

Novel control approaches for the next generation computer numerical control (CNC) system for hybrid micro-machines

It is well-recognised that micro-machining is a key enabling technology for manufacturing high value-added 3D micro-products, such as optics, moulds/dies and biomedical implants etc. These products are usually made of a wide range of engineering materials and possess complex freeform surfaces with tight tolerance on form accuracy and surface finish.In recent years, hybrid micro-machining technology has been developed to integrate several machining processes on one platform to tackle the manufacturing challenges for the aforementioned micro-products. However, the complexity of system integration and ever increasing demand for further enhanced productivity impose great challenges on current CNC systems. This thesis develops, implements and evaluates three novel control approaches to overcome the identified three major challenges, i.e. system integration, parametric interpolation and toolpath smoothing. These new control approaches provide solid foundation for the development of next generation CNC system for hybrid micro-machines.There is a growing trend for hybrid micro-machines to integrate more functional modules. Machine developers tend to choose modules from different vendors to satisfy the performance and cost requirements. However, those modules often possess proprietary hardware and software interfaces and the lack of plug-and-play solutions lead to tremendous difficulty in system integration. This thesis proposes a novel three-layer control architecture with component-based approach for system integration. The interaction of hardware is encapsulated into software components, while the data flow among different components is standardised. This approach therefore can significantly enhance the system flexibility. It has been successfully verified through the integration of a six-axis hybrid micro-machine. Parametric curves have been proven to be the optimal toolpath representation method for machining 3D micro-products with freeform surfaces, as they can eliminate the high-frequency fluctuation of feedrate and acceleration caused by the discontinuity in the first derivatives along linear or circular segmented toolpath. The interpolation for parametric curves is essentially an optimization problem, which is extremely difficult to get the time-optimal solution. This thesis develops a novel real-time interpolator for parametric curves (RTIPC), which provides a near time-optimal solution. It limits the machine dynamics (axial velocities, axial accelerations and jerk) and contour error through feedrate lookahead and acceleration lookahead operations. Experiments show that the RTIPC can simplify the coding significantly, and achieve up to ten times productivity than the industry standard linear interpolator. Furthermore, it is as efficient as the state-of-the-art Position-Velocity-Time (PVT) interpolator, while achieving much smoother motion profiles.Despite the fact that parametric curves have huge advantage in toolpath continuity, linear segmented toolpath is still dominantly used on the factory floor due to its straightforward coding and excellent compatibility with various CNC systems. This thesis presents a new real-time global toolpath smoothing algorithm, which bridges the gap in toolpath representation for CNC systems. This approach uses a cubic B-spline to approximate a sequence of linear segments. The approximation deviation is controlled by inserting and moving new control points on the control polygon. Experiments show that the proposed approach can increase the productivity by more than three times than the standard toolpath traversing algorithm, and 40% than the state-of-the-art corner blending algorithm, while achieving excellent surface finish.Finally, some further improvements for CNC systems, such as adaptive cutting force control and on-line machining parameters adjustment with metrology, are discussed in the future work section.It is well-recognised that micro-machining is a key enabling technology for manufacturing high value-added 3D micro-products, such as optics, moulds/dies and biomedical implants etc. These products are usually made of a wide range of engineering materials and possess complex freeform surfaces with tight tolerance on form accuracy and surface finish.In recent years, hybrid micro-machining technology has been developed to integrate several machining processes on one platform to tackle the manufacturing challenges for the aforementioned micro-products. However, the complexity of system integration and ever increasing demand for further enhanced productivity impose great challenges on current CNC systems. This thesis develops, implements and evaluates three novel control approaches to overcome the identified three major challenges, i.e. system integration, parametric interpolation and toolpath smoothing. These new control approaches provide solid foundation for the development of next generation CNC system for hybrid micro-machines.There is a growing trend for hybrid micro-machines to integrate more functional modules. Machine developers tend to choose modules from different vendors to satisfy the performance and cost requirements. However, those modules often possess proprietary hardware and software interfaces and the lack of plug-and-play solutions lead to tremendous difficulty in system integration. This thesis proposes a novel three-layer control architecture with component-based approach for system integration. The interaction of hardware is encapsulated into software components, while the data flow among different components is standardised. This approach therefore can significantly enhance the system flexibility. It has been successfully verified through the integration of a six-axis hybrid micro-machine. Parametric curves have been proven to be the optimal toolpath representation method for machining 3D micro-products with freeform surfaces, as they can eliminate the high-frequency fluctuation of feedrate and acceleration caused by the discontinuity in the first derivatives along linear or circular segmented toolpath. The interpolation for parametric curves is essentially an optimization problem, which is extremely difficult to get the time-optimal solution. This thesis develops a novel real-time interpolator for parametric curves (RTIPC), which provides a near time-optimal solution. It limits the machine dynamics (axial velocities, axial accelerations and jerk) and contour error through feedrate lookahead and acceleration lookahead operations. Experiments show that the RTIPC can simplify the coding significantly, and achieve up to ten times productivity than the industry standard linear interpolator. Furthermore, it is as efficient as the state-of-the-art Position-Velocity-Time (PVT) interpolator, while achieving much smoother motion profiles.Despite the fact that parametric curves have huge advantage in toolpath continuity, linear segmented toolpath is still dominantly used on the factory floor due to its straightforward coding and excellent compatibility with various CNC systems. This thesis presents a new real-time global toolpath smoothing algorithm, which bridges the gap in toolpath representation for CNC systems. This approach uses a cubic B-spline to approximate a sequence of linear segments. The approximation deviation is controlled by inserting and moving new control points on the control polygon. Experiments show that the proposed approach can increase the productivity by more than three times than the standard toolpath traversing algorithm, and 40% than the state-of-the-art corner blending algorithm, while achieving excellent surface finish.Finally, some further improvements for CNC systems, such as adaptive cutting force control and on-line machining parameters adjustment with metrology, are discussed in the future work section

SIRU development. Volume 1: System development

A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results

Hardware emulation of wireless communication fading channels

This dissertation investigates several main challenges to implementing hardware-based wireless fading channel emulators with emphasis on incorporating accurate correlation properties. Multiple-input multiple-output (MIMO) fading channels are usually triply-selective with three types of correlation: temporal correlation, inter-tap correlation, and spatial correlation. The proposed emulators implement the triply-selective fading Channel Impulse Response (CIR) by incorporating the three types of correlation into multiple uncorrelated frequency-flat Rayleigh fading waveforms while meeting real-time requirements for high data-rate, large-sized MIMO, and/or long CIR channels. Specifically, mixed parallel-serial computational structures are implemented for Kronecker products of the correlation matrices, which makes the best tradeoff between computational speed and hardware usage. Five practical fading channel examples are implemented for RF or underwater acoustic MIMO applications. The performance of the hardware emulators are verified with an Altera Field-Programmable Gate Array (FPGA) platform and the results match the software simulators in terms of statistical and correlation properties. The dissertation also contributes to the development of a 2-by-2 MIMO transceiver testbench that is used to measure real-world fading channels. Intensive channel measurements are performed for indoor fixed mobile-to-mobile channels and the estimated CIRs demonstrate the triply-selective correlation properties --Abstract, page iv