A survey on RF and microwave doherty power amplifier for mobile handset applications

This survey addresses the cutting-edge load modulation microwave and radio frequency power amplifiers for next-generation wireless communication standards. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. Moreover, advance design architectures for enhancing the Doherty power amplifier’s performance in terms of higher efficiency and wider bandwidth characteristics, as well as the compact design techniques of Doherty amplifier that meets the requirements of legacy 5G handset applications, will be discussed.Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-RFundação para a Ciência e a Tecnologia | Ref. UIDP/50008/201

Analysis of Internally Bandlimited Multistage Cubic-Term Generators for RF Receivers

Adaptive feedforward error cancellation applied to correct distortion arising from third-order nonlinearities in RF receivers requires low-noise low-power reference cubic nonidealities. Multistage cubic-term generators utilizing cascaded nonlinear operations are ideal in this regard, but the frequency response of the interstage circuitry can introduce errors into the cubing operation. In this paper, an overview of the use of cubic-term generators in receivers relative to other applications is presented. An interstage frequency response plan is presented for a receiver cubic-term generator and is shown to function for arbitrary three-signal third-order intermodulation generation. The noise of such circuits is also considered and is shown to depend on the total incoming signal power across a particular frequency band. Finally, the effects of the interstage group delay are quantified in the context of a relevant communication standard requirement

Bandwidth Enhancement Technique for Bipolar Single Stage Distributed Amplifier Design

This work reports a novel approach to extending the bandwidth of single stage distributed amplifiers (SSDAs). The three-stepped technique involves scaling down the inductance on the input artificial transmission line (ATL); creating a high frequency resonance peak by the addition of shunt capacitance on the input ATL; and compensating for the resulting increased reflection with adapted negative resistance attenuation compensation techniques. Compared with the inductive-peaked cascode technique applied in the SSDA which currently has the highest reported bandwidth, simulation results, based on full foundry transistor models, predict up to 30% improvement in gain-bandwidth (GBW) performance for the same active device at the same bias. In addition, the reduction in the length of the input ATL effectively reduces transmission line losses, thereby improving the overall gain performance

Qualitative Analysis of Darlington Feedback Amplifier at 45nm Technology

The transistors are the key element of present communication system having high data rate. Some applications need high gain by using very low frequency, and then transistors are used. Amplifier is the key element in many applications of present high data rate communication system such as low noise amplifier (LNA), broadband amplifier, distributed and power amplifier. The Darlington pair amplifier is analyzed for high frequency performance and related effect of bandwidth. Broadband feedback Darlington pair amplifier is designed with enhanced gain, bandwidth and slew rate. This paper presents the comparison of single stage and three stage feedback Darlington feedback amplifier with reference to gain, bandwidth and slew rate. This paper is simulated on cadence analog design environment at GPDK 45nm technology. This paper shows that increase in gain, bandwidth and slew rate of three stage Darlington feedback amplifier can show better stability over the single stage Darlington feedback amplifier.

High-Efficiency Doherty-Based Power Amplifiers Using GaN Technology For Wireless Infrastructure Applications

abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Design, construction and evaluation of a 12.2 GHz, 4.0 kW-CW high efficiency klystron amplifier

An analytical and experimental program is described, for studying design techniques for optimizing the conversion efficiency of klystron amplifiers, and to utilize these techniques in the development and fabrication of an X-band 4 kW cw klystron, for use in satellite-borne television broadcast transmitters. The design is based on a technique for increasing the RF beam current by using the second harmonic space charge forces in the bunched beam. Experimental analysis was also made of a method to enhance circuit efficiency in the klystron cavities. The design incorporates a collector which is demountable from the tube to facilitate multistage depressed collector experiments employing an axisymmetric, electrostatic collector for linear beam microwave tubes

Advanced design features of Doherty power amplifiers

A Doherty power amplifier (DPA) is an effective structure born in 1936 which, after a scarce revival around year 2000), had been strengthened from 2005 because its capability to combine linear amplification with power efficiency. Despite the conceptual simplicity of its basic operation, a lot of practical drawbacks shrink the theoretical behavior, thus leading a significant number of research works to overcome them. The main objective in DPA research is to increase efficiency while maintaining linearity and filling the specified bandwidth. This paper presents a survey of the state of the art of DPA advanced design aspects. After a short review of the DPA operation principles, aspects regarding improvements for linearity, power efficiency and amplification bandwidth are introduced. Besides, some alternative structures and technologies, as well as practical design aspects and some trade-offs which the designer usually has to face are also presented.Peer ReviewedPostprint (published version

Analytical study program to develop the theoretical design of traveling-wave tubes Final report

Design study to develop high efficiency traveling wave tube amplifier for satellite television transmissio

High performance CMOS integrated circuits for optical receivers

Optical communications is expanding into new applications such as infrared wireless communications; therefore, designing high performance circuits has gained considerable importance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier (TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operational transconductance amplifier (OTA) as the feed forward gain element to control gain and improve the overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35µm CMOS technology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from 6µA-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1kΩ to 3kΩ, -3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The power dissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively. A new technique for designing uniform multistage amplifiers (MA) for high frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. It has several advantages, such as tunability of bandwidth and decreased sensitivity of amplifier stages, to process variations. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Two six-stage amplifiers in a TSMC 0.35µm CMOS process were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for the second one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/√Hz noise. Although the second amplifier has a higher gain bandwidth product, it consumes more power and occupies a wider area. A technique for capacitance multiplication is utilized to design a tunable loop filter. Current and voltage mode techniques are combined to increase the multiplication factor (M). At a high input dynamic range, M is adjustable and the capacitance multiplier performs linearly at high frequencies. Drain-source voltages of paired transistors are equalized to improve matching in the current mirrors. Measurement of a prototype loop filter IC in a 0.5µm CMOS technology shows 50µA current consumption for M=50. Where 80pF capacitance is employed, the capacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF