Near-Instantaneously Adaptive HSDPA-Style OFDM Versus MC-CDMA Transceivers for WIFI, WIMAX, and Next-Generation Cellular Systems

Burts-by-burst (BbB) adaptive high-speed downlink packet access (HSDPA) style multicarrier systems are reviewed, identifying their most critical design aspects. These systems exhibit numerous attractive features, rendering them eminently eligible for employment in next-generation wireless systems. It is argued that BbB-adaptive or symbol-by-symbol adaptive orthogonal frequency division multiplex (OFDM) modems counteract the near instantaneous channel quality variations and hence attain an increased throughput or robustness in comparison to their fixed-mode counterparts. Although they act quite differently, various diversity techniques, such as Rake receivers and space-time block coding (STBC) are also capable of mitigating the channel quality variations in their effort to reduce the bit error ratio (BER), provided that the individual antenna elements experience independent fading. By contrast, in the presence of correlated fading imposed by shadowing or time-variant multiuser interference, the benefits of space-time coding erode and it is unrealistic to expect that a fixed-mode space-time coded system remains capable of maintaining a near-constant BER

Interference-Mitigating Waveform Design for Next-Generation Wireless Systems

A brief historical perspective of the evolution of waveform designs employed in consecutive generations of wireless communications systems is provided, highlighting the range of often conflicting demands on the various waveform characteristics. As the culmination of recent advances in the field the underlying benefits of various Multiple Input Multiple Output (MIMO) schemes are highlighted and exemplified. As an integral part of the appropriate waveform design, cognizance is given to the particular choice of the duplexing scheme used for supporting full-duplex communications and it is demonstrated that Time Division Duplexing (TDD) is substantially outperformed by Frequency Division Duplexing (FDD), unless the TDD scheme is combined with further sophisticated scheduling, MIMOs and/or adaptive modulation/coding. It is also argued that the specific choice of the Direct-Sequence (DS) spreading codes invoked in DS-CDMA predetermines the properties of the system. It is demonstrated that a specifically designed family of spreading codes exhibits a so-called interference-free window (IFW) and hence the resultant system is capable of outperforming its standardised counterpart employing classic Orthogonal Variable Spreading Factor (OVSF) codes under realistic dispersive channel conditions, provided that the interfering multi-user and multipath components arrive within this IFW. This condition may be ensured with the aid of quasisynchronous adaptive timing advance control. However, a limitation of the system is that the number of spreading codes exhibiting a certain IFW is limited, although this problem may be mitigated with the aid of novel code design principles, employing a combination of several spreading sequences in the time-frequency and spatial-domain. The paper is concluded by quantifying the achievable user load of a UTRA-like TDD Code Division Multiple Access (CDMA) system employing Loosely Synchronized (LS) spreading codes exhibiting an IFW in comparison to that of its counterpart using OVSF codes. Both system's performance is enhanced using beamforming MIMOs

Labeling Diversity for 2x2 WLAN Coded-Cooperative Networks

Labelling diversity is an efficient technique recently proposed in the literature and aims to improve the bit error rate(BER) performance of wireless local area network (WLAN) systems with two transmit and two receive antennas without increasing the transmit power and bandwidth requirements. In this paper, we employ labelling diversity with different space-time channel codes such as convolutional, turbo and low density parity check (LDPC) for both point-to-point and coded-cooperative communication scenarios. Joint iterative decoding schemes for distributed turbo and LDPC codes are also presented. BER performance bounds at an error floor (EF) region are derived and verified with the help of numerical simulations for both cooperative and non-cooperative schemes. Numerical simulations show that the coded-cooperative schemes with labelling diversity achieve better BER performances and use of labelling diversity at the source node significantly lowers relay outage probability and hence the overall BER performance of the coded-cooperative scheme is improved manifolds

Evaluation of cross-layer reliability mechanisms for satellite digital multimedia broadcast

This paper presents a study of some reliability mechanisms which may be put at work in the context of Satellite Digital Multimedia Broadcasting (SDMB) to mobile devices such as handheld phones. These mechanisms include error correcting codes, interleaving at the physical layer, erasure codes at intermediate layers and error concealment on the video decoder. The evaluation is made on a realistic satellite channel and takes into account practical constraints such as the maximum zapping time and the user mobility at several speeds. The evaluation is done by simulating different scenarii with complete protocol stacks. The simulations indicate that, under the assumptions taken here, the scenario using highly compressed video protected by erasure codes at intermediate layers seems to be the best solution on this kind of channel

Bilayer Protograph Codes for Half-Duplex Relay Channels

Despite encouraging advances in the design of relay codes, several important challenges remain. Many of the existing LDPC relay codes are tightly optimized for fixed channel conditions and not easily adapted without extensive re-optimization of the code. Some have high encoding complexity and some need long block lengths to approach capacity. This paper presents a high-performance protograph-based LDPC coding scheme for the half-duplex relay channel that addresses simultaneously several important issues: structured coding that permits easy design, low encoding complexity, embedded structure for convenient adaptation to various channel conditions, and performance close to capacity with a reasonable block length. The application of the coding structure to multi-relay networks is demonstrated. Finally, a simple new methodology for evaluating the end-to-end error performance of relay coding systems is developed and used to highlight the performance of the proposed codes.Comment: Accepted in IEEE Trans. Wireless Com

Implementable Wireless Access for B3G Networks - III: Complexity Reducing Transceiver Structures

This article presents a comprehensive overview of some of the research conducted within Mobile VCE’s Core Wireless Access Research Programme,1 a key focus of which has naturally been on MIMO transceivers. The series of articles offers a coherent view of how the work was structured and comprises a compilation of material that has been presented in detail elsewhere (see references within the article). In this article MIMO channel measurements, analysis, and modeling, which were presented previously in the first article in this series of four, are utilized to develop compact and distributed antenna arrays. Parallel activities led to research into low-complexity MIMO single-user spacetime coding techniques, as well as SISO and MIMO multi-user CDMA-based transceivers for B3G systems. As well as feeding into the industry’s in-house research program, significant extensions of this work are now in hand, within Mobile VCE’s own core activity, aiming toward securing major improvements in delivery efficiency in future wireless systems through crosslayer operation

System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Distributed video coding for wireless video sensor networks: a review of the state-of-the-art architectures

Distributed video coding (DVC) is a relatively new video coding architecture originated from two fundamental theorems namely, Slepian–Wolf and Wyner–Ziv. Recent research developments have made DVC attractive for applications in the emerging domain of wireless video sensor networks (WVSNs). This paper reviews the state-of-the-art DVC architectures with a focus on understanding their opportunities and gaps in addressing the operational requirements and application needs of WVSNs