1,439 research outputs found
Physical Design and Clock Tree Synthesis Methods For A 8-Bit Processor
Now days a number of processors are available with a lot kind of feature from different industries. A processor with similar kind of architecture of the current processors only missing the memory stuffs like the RAM and ROM has been designed here with the help of Verilog style of coding. This processor contains architecturally the program counter, instruction register, ALU, ALU latch, General Purpose Registers, control state module, flag registers and the core module containing all the modules. And a test module is designed for testing the processor. After the design of the processor with successful functionality, the processor is synthesized with 180nm technology. The synthesis is performed with the data path optimization like the selection of proper adders and multipliers for timing optimization in the data path while the ALU operations are performed. During synthesis how to take care of the worst negative slack (WNS), how to include the clock gating cells, how to define the cost and path groups etc. have been covered. After the proper synthesis we get the proper net list and the synthesized constraint file for carrying out the physical design. In physical design the steps like floor-planning, partitioning, placement, legalization of the placement, clock tree synthesis, and routing etc. have been performed. At all the stages the static timing analysis is performed for the timing meet of the design for better performance in terms of timing or frequency. Each steps of physical design are discussed with special effort towards the concepts behind the step. Out of all the steps of physical design the clock tree synthesis is performed with some improvement in the performance of the clock tree by creating a symmetrical clock tree and maintaining more common clock paths. A special algorithm has been framed for creating a symmetrical clock tree and thereby making the power consumption of the clock tree low
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μ μμ§μΈλ€.Timing analysis and clearing design rule violations are the essential steps for taping out a chip. However, they keep getting harder in deep sub-micron circuits because the variations of transistors and interconnects have been increasing and design rules have become more complex. This dissertation addresses two problems on timing analysis and design rule violations for synthesizing deep sub-micron circuits.
Firstly, timing analysis in process corners can not capture post-Si performance accurately because the slowest path in the process corner is not always the slowest one in the post-Si instances. In addition, the proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical
path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (backend-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To cope with this, I propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, the
synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of this work.
Secondly, the complexity of design rules has been increasing and results in more design rule violations during routing. In addition, the size of standard cell keeps decreasing and it makes routing harder. In the conventional P&R flow, the routability of pre-routed layout is predicted by routing congestion obtained from global routing, and then placement is optimized not to cause design rule violations. But it turned out to be inaccurate in advanced technology nodes so that it is necessary to predict routability with more features. I propose a methodology of predicting the hotspots of design rule violations (DRVs) using machine learning with placement related features and the conventional routing congestion, and perturbating placed cells to reduce the number of DRVs. Precisely, the hotspots are predicted by a pre-trained binary classification model and placement perturbation is performed by global optimization methods to minimize the number of DRVs predicted by a pre-trained regression model. To do this, the framework is composed of three techniques: (1) dividing the circuit layout into multiple rectangular grids and extracting features such as pin density, cell density, global routing results (demand, capacity and overflow), and more in the placement phase, (2) predicting if each grid has DRVs using a binary classification model, and (3) perturbating the placed standard cells in the hotspots to minimize the number of DRVs predicted by a regression model.1 Introduction 1
1.1 Representative Critical Path Circuit . . . . . . . . . . . . . . . . . . . 1
1.2 Prediction of Design Rule Violations and Placement Perturbation . . . 5
1.3 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . 7
2 Methodology for Synthesizing Representative Critical Path Circuits reflecting BEOL Timing Variation 9
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Definitions and Overall Flow . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Techniques for BEOL-Aware RCP Generation . . . . . . . . . . . . . 17
2.3.1 Clustering BEOL Configurations . . . . . . . . . . . . . . . . 17
2.3.2 Formulating Statistical BEOL Random Variables . . . . . . . 18
2.3.3 Delay Modeling . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.4 Exploring Ring Oscillator Circuit Structures . . . . . . . . . . 24
2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 Further Study on Variations . . . . . . . . . . . . . . . . . . . . . . . 37
3 Methodology for Reducing Routing Failures through Enhanced Prediction on Design Rule Violations in Placement 39
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 Techniques for Reducing Routing Failures . . . . . . . . . . . . . . . 43
3.3.1 Binary Classification . . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 47
3.4 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.1 Experiments Setup . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.2 Hotspot Prediction . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.3 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 57
4 Conclusions 61
4.1 Synthesis of Representative Critical Path Circuits reflecting BEOL Timing Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Reduction of Routing Failures through Enhanced Prediction on Design Rule Violations in Placement . . . . . . . . . . . . . . . . . . . . . . 62
Abstract (In Korean) 69Docto
A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries
Engineering andPhysical Science ResearchCouncil
(EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt
to improve standard cell libraries aimed at operation in the subthreshold regime and in
Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is
examined, with particular emphasis on how subthreshold physical effects degrade
robustness, variability and performance. How prevalent these physical effects are in a
commercial 65nm library is then investigated by extensive modeling of a BSIM4.5
compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out
and post-layout parasitically extracted models simulated to determine the
advantages/disadvantages of each. Full custom ring oscillators are designed and
manufactured. Measured results reveal a close correlation with the simulated results, with
frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices
respectively. The experiment provides the first silicon evidence of the improvement
capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well
as a mechanism of additional temperature stability in the subthreshold regime.
A novel sizing strategy is proposed and pursued to determine whether it is able to produce
a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit
AES cores are synthesized from the novel sizing strategy and compared against a third
AES core synthesized from a state-of-the-art subthreshold standard cell library used by
ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency
improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior
over a temperature range of 0 Β°C to 85 Β°C with a nominal (20 Β°C) improvement in
energy-per-cycle of 24% and frequency improvement of 8.65X.
A comparison to prior art is then performed. Valid cases are presented where the
proposed sizing strategy would be a candidate to produce superior subthreshold circuits
HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS
Tohoku Universityε ε£ ι²θͺ²
Evaluation of temperature-performance trade-offs in wireless network-on-chip architectures
Continued scaling of device geometries according to Moore\u27s Law is enabling complete end-user systems on a single chip. Massive multicore processors are enablers for many information and communication technology (ICT) innovations spanning various domains, including healthcare, defense, and entertainment. In the design of high-performance massive multicore chips, power and heat are dominant constraints. Temperature hotspots witnessed in multicore systems exacerbate the problem of reliability in deep submicron technologies. Hence, there is a great need to explore holistic power and thermal optimization and management strategies for the massive multicore chips. High power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. Thus, addressing thermal concerns at different stages of the design and operation is critical to the success of future generation systems. The performance of a multicore chip is also influenced by its overall communication infrastructure, which is predominantly a Network-on-Chip (NoC). The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency, significant power consumption, and temperature hotspots arising out of long, multi-hop wireline links used in data exchange. On-chip wireless networks are envisioned as an enabling technology to design low power and high bandwidth massive multicore architectures. However, optimizing wireless NoCs for best performance does not necessarily guarantee a thermally optimal interconnection architecture. The wireless links being highly efficient attract very high traffic densities which in turn results in temperature hotspots. Therefore, while the wireless links result in better performance and energy-efficiency, they can also cause temperature hotspots and undermine the reliability of the system. Consequently, the location and utilization of the wireless links is an important factor in thermal optimization of high performance wireless Networks-on-Chip. Architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance yet energy-efficient massive multicore chips. This work contributes to exploration of various the design methodologies for establishing wireless NoC architectures that achieve the best trade-offs between temperature, performance and energy-efficiency. It further demonstrates that incorporating Dynamic Thermal Management (DTM) on a multicore chip designed with such temperature and performance optimized Wireless Network-on-Chip architectures improves thermal profile while simultaneously providing lower latency and reduced network energy dissipation compared to its conventional counterparts
Modeling and Analysis of Large-Scale On-Chip Interconnects
As IC technologies scale to the nanometer regime, efficient and accurate modeling
and analysis of VLSI systems with billions of transistors and interconnects becomes
increasingly critical and difficult. VLSI systems impacted by the increasingly high
dimensional process-voltage-temperature (PVT) variations demand much more modeling
and analysis efforts than ever before, while the analysis of large scale on-chip
interconnects that requires solving tens of millions of unknowns imposes great challenges
in computer aided design areas. This dissertation presents new methodologies
for addressing the above two important challenging issues for large scale on-chip interconnect
modeling and analysis:
In the past, the standard statistical circuit modeling techniques usually employ
principal component analysis (PCA) and its variants to reduce the parameter
dimensionality. Although widely adopted, these techniques can be very
limited since parameter dimension reduction is achieved by merely considering
the statistical distributions of the controlling parameters but neglecting
the important correspondence between these parameters and the circuit performances
(responses) under modeling. This dissertation presents a variety of
performance-oriented parameter dimension reduction methods that can lead to
more than one order of magnitude parameter reduction for a variety of VLSI
circuit modeling and analysis problems.
The sheer size of present day power/ground distribution networks makes their
analysis and verification tasks extremely runtime and memory inefficient, and
at the same time, limits the extent to which these networks can be optimized.
Given today?s commodity graphics processing units (GPUs) that can deliver
more than 500 GFlops (Flops: floating point operations per second). computing
power and 100GB/s memory bandwidth, which are more than 10X greater
than offered by modern day general-purpose quad-core microprocessors, it is
very desirable to convert the impressive GPU computing power to usable design
automation tools for VLSI verification. In this dissertation, for the first time, we
show how to exploit recent massively parallel single-instruction multiple-thread
(SIMT) based graphics processing unit (GPU) platforms to tackle power grid
analysis with very promising performance. Our GPU based network analyzer
is capable of solving tens of millions of power grid nodes in just a few seconds.
Additionally, with the above GPU based simulation framework, more challenging
three-dimensional full-chip thermal analysis can be solved in a much more
efficient way than ever before
Multivariate Adaptive Regression Splines in Standard Cell Characterization for Nanometer Technology in Semiconductor
Multivariate adaptive regression splines (MARSP) is a nonparametric regression method. It is an adaptive procedure which does not have any predetermined regression model. With that said, the model structure of MARSP is constructed dynamically and adaptively according to the information derived from the data. Because of its ability to capture essential nonlinearities and interactions, MARSP is considered as a great fit for high-dimension problems. This chapter gives an application of MARSP in semiconductor field, more specifically, in standard cell characterization. The objective of standard cell characterization is to create a set of high-quality models of a standard cell library that accurately and efficiently capture cell behaviors. In this chapter, the MARSP method is employed to characterize the gate delay as a function of many parameters including process-voltage-temperature parameters. Due to its ability of capturing essential nonlinearities and interactions, MARSP method helps to achieve significant accuracy improvement
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Network-on-Chip Synchronization
Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of βbrute-forceβ synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency.
First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed.
To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers
FinFET Cell Library Design and Characterization
abstract: Modern-day integrated circuits are very capable, often containing more than a billion transistors. For example, the Intel Ivy Bridge 4C chip has about 1.2 billion transistors on a 160 mm2 die. Designing such complex circuits requires automation. Therefore, these designs are made with the help of computer aided design (CAD) tools. A major part of this custom design flow for application specific integrated circuits (ASIC) is the design of standard cell libraries. Standard cell libraries are a collection of primitives from which the automatic place and route (APR) tools can choose a collection of cells and implement the design that is being put together. To operate efficiently, the CAD tools require multiple views of each cell in the standard cell library. This data is obtained by characterizing the standard cell libraries and compiling the results in formats that the tools can easily understand and utilize.
My thesis focusses on the design and characterization of one such standard cell library in the ASAP7 7 nm predictive design kit (PDK). The complete design flow, starting from the choice of the cell architecture, design of the cell layouts and the various decisions made in that process to obtain optimum results, to the characterization of those cells using the Liberate tool provided by Cadence design systems Inc., is discussed in this thesis. The end results of the characterized library are used in the APR of a few open source register-transfer logic (RTL) projects and the efficiency of the library is demonstrated.Dissertation/ThesisMasters Thesis Computer Engineering 201
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