Design Techniques of Highly Integrated Hybrid-Switched-Capacitor-Resonant Power Converters for LED Lighting Applications

The Light-emitting diodes (LEDs) are rapidly emerging as the dominant light source given their high luminous efficacy, long lift span, and thanks to the newly enacted efficiency standards in favor of the more environmentally-friendly LED technology. The LED lighting market is expected to reach USD 105.66 billion by 2025. As such, the lighting industry requires LED drivers, which essentially are power converters, with high efficiency, wide input/output range, low cost, small form factor, and great performance in power factor, and luminance flicker. These requirements raise new challenges beyond the traditional power converter topologies. On the other hand, the development and improvement of new device technologies such as printed thin-film capacitors and integrated high voltage/power devices opens up many new opportunities for mitigating such challenges using innovative circuit design techniques and solutions. Almost all electric products needs certain power delivery, regulation or conversion circuits to meet the optimized operation conditions. Designing a high performance power converter is a real challenge given the market’s increasing requirements on energy efficiency, size, cost, form factor, EMI performance, human health impact, and so on. The design of a LED driver system covers from high voltage AC/DC and DC/DC power converters, to high frequency low voltage digital controllers, to power factor correction (PFC) and EMI filtering techniques, and to safety solutions such as galvanic isolation. In this thesis, we study design challenges and present corresponding solutions to realize highly integrated and high performance LED drivers combining switched-capacitor and resonant converters, applying re-configurable multi-level circuit topology, utilizing sigma delta modulation, and exploring capacitive galvanic isolation. A hybrid switched-capacitor-resonant (HSCR) LED driver based on a stackable switched-capacitor (SC) converter IC rated for 15 to 20 W applications. Bulky transformers have been replaced with a SC ladder to perform high-efficiency voltage step-down conversion; an L-C resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120 V silicon technology. The LED driver demonstrates > 91% efficiency over a rectified input DC voltage range from 160 VDC to 180 VDC with two stacked ICs; using a stack of four ICs > 89.6% efficiency is demonstrated over an input range from 320 VDC to 360 VDC . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a PWM controlled clock gating circuit. Next, the design of AC main rectifier and inverter front end with sigma delta modulation is described. The proposed circuits features a pair of sigma delta controlled multilevel converters. The first is a multilevel rectifier responsible for PFC and dimming. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications

Intelligent LED Display

The goal of this project is to increase the overall redundancy, and ease-of-use during installation and operation, of large-format LED video displays for the professional touring and outdoor display industry. Using design concepts found in large-scale redundant networks, the system dynamically scales video output to the LED display and provides adaptive real-time fault detection and failover behaviors to ensure reliability in rigorous outdoor environments. This ultimately simplifies installation of a system, eliminating the need for the individual addressing of panels and alignment of video content. The designed system is inherently redundant and the ability to sustain failure of its components increases with the size of the display making it ideal for live applications

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation

Hybrid monolithic integration of high-power DC-DC converters in a high-voltage technology

The supply of electrical energy to home, commercial, and industrial users has become ubiquitous, and it is hard to imagine a world without the facilities provided by electrical energy. Despite the ever increasing efficiency of nearly every electrical application, the worldwide demand for electrical power continues to increase, since the number of users and applications more than compensates for these technological improvements. In order to maintain the affordability and feasibility of the total production, it is essential for the distribution of the produced electrical energy to be as efficient as possible. In other words the loss in the power distribution is to be minimized. By transporting electrical energy at the maximum safe voltage, the current in the conductors, and the associated conduction loss can remain as low as possible. In order to optimize the total efficiency, the high transportation voltage needs to be converted to the appropriate lower voltage as close as possible to the end user. Obviously, this conversion also needs to be as efficient, affordable, and compact as possible. Because of the ever increasing integration of electronic systems, where more and more functionality is combined in monolithically integrated circuits, the cost, the power consumption, and the size of these electronic systems can be greatly reduced. This thorough integration is not limited to the electronic systems that are the end users of the electrical energy, but can also be applied to the power conversion itself. In most modern applications, the voltage conversion is implemented as a switching DC-DC converter, in which electrical energy is temporarily stored in reactive elements, i.e. inductors or capacitors. High switching speeds are used to allow for a compact and efficient implementation. For low power levels, typically below 1 Watt, it is possible to monolithically implement the voltage conversion on an integrated circuit. In some cases, this is even done on the same integrated circuit that is the end user of the electrical energy to minimize the system dimensions. For higher power levels, it is no longer feasible to achieve the desired efficiency with monolithically integrated components, and some external components prove indispensable. Usually, the reactive components are the main limiting factor, and are the first components to be moved away from the integrated circuit for increasing power levels. The semiconductor components, including the power transistors, remain part of the integrated circuit. Using this hybrid approach, it is possible in modern converterapplications to process around 60 Watt, albeit limited to voltages of a few Volt. For hybrid integrated converters with an output voltage of tens of Volt, the power is limited to approximately 10 Watt. For even higher power levels, the integrated power transistors also become a limiting factor, and are replaced with discrete power devices. In these discrete converters, greatly increased power levels become possible, although the system size rapidly increases. In this work, the limits of the hybrid approach are explored when using so-called smart-power technologies. Smart-power technologies are standard lowcost submicron CMOS technologies that are complemented with a number of integrated high-voltage devices. By using an appropriate combination of smart-power technologies and circuit topologies, it is possible to improve on the current state-of-the-art converters, by optimizing the size, the cost, and the efficiency. To determine the limits of smart-power DC-DC converters, we first discuss the major contributing factors for an efficient energy distribution, and take a look at the role of voltage conversion in the energy distribution. Considering the limitations of the technologies and the potential application areas, we define two test-cases in the telecommunications sector for which we want to optimize the hybrid monolithic integration in a smart-power technology. Subsequently, we explore the specifications of an ideal converter, and the relevant properties of the affordable smart-power technologies for the implementation of DC-DC converters. Taking into account the limitations of these technologies, we define a cost function that allows to systematically evaluate the different potential converter topologies, without having to perform a full design cycle for each topology. From this cost function, we notice that the de facto default topology selection in discrete converters, which is typically based on output power, is not optimal for converters with integrated power transistors. Based on the cost function and the boundary conditions of our test-cases, we determine the optimal topology for a smart-power implementation of these applications. Then, we take another step towards the real world and evaluate the influence of parasitic elements in a smart-power implementation of switching converters. It is noticed that the voltage overshoot caused by the transformer secondary side leakage inductance is a major roadblock for an efficient implementation. Since the usual approach to this voltage overshoot in discrete converters is not applicable in smart-power converters due to technological limitations, an alternative approach is shown and implemented. The energy from the voltage overshoot is absorbed and transferred to the output of the converter. This allows for a significant reduction in the voltage overshoot, while maintaining a high efficiency, leading to an efficient, compact, and low-cost implementation. The effectiveness of this approach was tested and demonstrated in both a version using a commercially available integrated circuit, and our own implementation in a smart-power integrated circuit. Finally, we also take a look at the optimization of switching converters over the load range by exploiting the capabilities of highly integrated converters. Although the maximum output power remains one of the defining characteristics of converters, it has been shown that most converters spend a majority of their lifetime delivering significantly lower output power. Therefore, it is also desirable to optimize the efficiency of the converter at reduced output current and output power. By splitting the power transistors in multiple independent segments, which are turned on or off in function of the current, the efficiency at low currents can be significantly improved, without introducing undesirable frequency components in the output voltage, and without harming the efficiency at higher currents. These properties allow a near universal application of the optimization technique in hybrid monolithic DC-DC converter applications, without significant impact on the complexity and the cost of the system. This approach for the optimization of switching converters over the load range was demonstrated using a boost converter with discrete power transistors. The demonstration of our smart-power implementation was limited to simulations due to an issue with a digital control block. On a finishing note, we formulate the general conclusions and provide an outlook on potential future work based on this research

LED Jitter-Induced Limitation Effects in the Baud Rate of VLC

In this paper we show that the effect of jitter due to driver and LED is the limiting factor in the baud rate in L-PPM formats for VLC systems

A Novel Boost Converter Based LED Driver Chip Targeting Mobile Applications

abstract: A novel integrated constant current LED driver design on a single chip is developed in this dissertation. The entire design consists of two sections. The first section is a DC-DC switching regulator (boost regulator) as the frontend power supply; the second section is the constant current LED driver system. In the first section, a pulse width modulated (PWM) peak current mode boost regulator is utilized. The overall boost regulator system and its related sub-cells are explained. Among them, an original error amplifier design, a current sensing circuit and slope compensation circuit are presented. In the second section – the focus of this dissertation – a highly accurate constant current LED driver system design is unveiled. The detailed description of this highly accurate LED driver system and its related sub-cells are presented. A hybrid PWM and linear current modulation scheme to adjust the LED driver output currents is explained. The novel design ideas to improve the LED current accuracy and channel-to-channel output current mismatch are also explained in detail. These ideas include a novel LED driver system architecture utilizing 1) a dynamic current mirror structure and 2) a closed loop structure to keep the feedback loop of the LED driver active all the time during both PWM on-duty and PWM off-duty periods. Inside the LED driver structure, the driving amplifier with a novel slew rate enhancement circuit to dramatically accelerate its response time is also presented.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Single-Chip Isolated DC-DC Converter with Self-Tuned Maximum Power Transfer Frequency

abstract: There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications. A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m^3 and is operated in a 0.5 T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb--Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report.Comment: 55 pages, 82 figure