57 research outputs found
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Complexity-reduced hardware-based track-trigger for CMS upgrade
This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University LondonThe Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC)
is designed to study the results of proton-proton collisions. The Tracker
sub-detector is designed to detect and reconstruct the trajectories of charged
particles produced by the collisions. During the lifetime of the CMS detector,
there have been several upgrades aimed at increasing the chance of discovering
new physics through increased luminosity levels and instrumentation of
advanced technology. The High-Luminosity upgrade optimises the LHC to
accelerate high-energy particles with an average of 200 proton-proton
interactions per bunch crossing. The Level-1 Trigger system promptly analyses
and filters collisions using hardware to reduce the data volume in real-time. For
the upgrade, the trigger mechanism will use a particle trajectory estimator that
discriminates between particles based on their transverse momentum (pT ).
Particles with pT ≥ 2 GeV/c will be transmitted to the Level-1 Track-Trigger
system for trajectory reconstruction within a fixed 3 μs latency. This thesis
presents a novel Hardware-based Multivariate Linear Fitter (MVLF) system
focusing on robustness in tracking efficiency and reduction in logic resource
usage within the specified latency. The system components are implemented in
Field Programmable Gate Arrays (FPGA), targeting 16 nm FinFET UltraScale+
silicon technology. The development was performed using the High-Level
Synthesis (HLS) automation tools and the Hardware acceleration platform for
Application-Specific Integrated Circuits (ASIC). A firmware demonstrator has
been assembled to verify the feasibility and compatibility of the scaled system
with the CMS Level-1 Track-Trigger infrastructure. The system’s performance is
compared to past and current system developments, and the results are
presented accordingly
Development of electronics for the VELO upgrade detector
Esta tesis cubre el diseño electrónico del detector de vértices (VELO) del
experimento LHCb del CERN. El VELO está situado rodeando el punto de colisión de los dos haces de protones
del LHC del CERN. Su diseño está lleno de restricciones que requieren diseños novedosos: minimizar la materia
cerca del punto de colisión, diseño de componentes que soporten radiación, transmisión de datos a alta tasa y el
procesado de los mismos, sincronización del sistema, etc. El trabajo presentado en esta tesis se centra en: por un
lado, la validación del hardware y sus diferentes prototipos, por otro lado, el diseño del firmware de las FPGAs
encargadas del control, sincronización y adquisición de datos del VELO
Designing periodic and aperiodic structures for nanophotinic devices.
330 p.Future all--optical networks will require to substitute the present electronic integrated circuitry by optical analogous devices that satisfy the compactness, throughput, latency and high transmission efficiency requirements in nanometer scale dimensions, outperforming the functionality of current networks. Thereby, existing dielectric materials do not confine light in a sufficiently small scale and so the physical size of these links and devices becomes unacceptable. In fact, if the optical chip does not exist in the liking of the electronic chip, photonic crystals have recently led to great hopes for a large-scale integration of optoelectronic components. Two-dimensional photonic crystals slabs obtained through periodic structuring of a planar optical waveguide, feature many characteristics which bring them closer to electronic micro-and nanostructures. This thesis explores non-trivial periodic and aperiodic dielectric nano-structures and to do so, we pose a photonic crystal design process guided by non-convex combinatory optimization techniques. In addition, this thesis proposes some novel coupling devices optimized to minimize insertion losses between silicon-on-insulator integrated waveguides and single mode optical fibers. Last but not least, this thesis explores periodic arrangements from a new perspective and reports on the first experimental evidence of topologically protected waveguiding in silicon. Furthermore, we propose and demonstrate that, in a system where topological and trivial defect modes coexist, we can probe them independently. Tuning the configuration of the interface, we observe the transition between a single topological defect and a compound trivial defect state
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Cross-Layer Pathfinding for Off-Chip Interconnects
Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects
Designing periodic and aperiodic structures for nanophotinic devices.
330 p.Future all--optical networks will require to substitute the present electronic integrated circuitry by optical analogous devices that satisfy the compactness, throughput, latency and high transmission efficiency requirements in nanometer scale dimensions, outperforming the functionality of current networks. Thereby, existing dielectric materials do not confine light in a sufficiently small scale and so the physical size of these links and devices becomes unacceptable. In fact, if the optical chip does not exist in the liking of the electronic chip, photonic crystals have recently led to great hopes for a large-scale integration of optoelectronic components. Two-dimensional photonic crystals slabs obtained through periodic structuring of a planar optical waveguide, feature many characteristics which bring them closer to electronic micro-and nanostructures. This thesis explores non-trivial periodic and aperiodic dielectric nano-structures and to do so, we pose a photonic crystal design process guided by non-convex combinatory optimization techniques. In addition, this thesis proposes some novel coupling devices optimized to minimize insertion losses between silicon-on-insulator integrated waveguides and single mode optical fibers. Last but not least, this thesis explores periodic arrangements from a new perspective and reports on the first experimental evidence of topologically protected waveguiding in silicon. Furthermore, we propose and demonstrate that, in a system where topological and trivial defect modes coexist, we can probe them independently. Tuning the configuration of the interface, we observe the transition between a single topological defect and a compound trivial defect state
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Layer assignment and routing optimization for advanced technologies
As VLSI technology scales to deep sub-micron and beyond, it becomes
increasingly challenging to achieve timing closure for VLSI design. Since a
complete design flow consists of several phases, such as logic synthesis, placement, and routing, interconnect synthesis plays an important role which includes buffer insertion/sizing and timing-driven routing. Although progress has been achieved by many advanced routing techniques, the following aspects
can be exploited sufficiently for further improvement: (1) incremental layer assignment for timing optimization; (2) signal routing with the requirement of regularity; (3) power-efficient optical-electrical interconnect paradigm. Thus, to perform the layer assignment and routing optimization for advanced technologies,
an automated routing engine in a global view is essential to benefit the interconnect design while satisfying specific requirements.
This dissertation proposes a set of algorithms and methodology on layer
assignment and routing optimization for advanced technologies. The research includes two timing-driven incremental layer assignment approaches, synergistic
topology generation and routing synthesis for signal groups, and optical-electrical routing design for power efficiency.
For incremental layer assignment, most of the conventional approaches
target via minimization but neglect the timing issues. Meanwhile, via delays
are ignored but should be considered in emerging technology nodes. Then two
timing-driven incremental layer assignment frameworks are proposed, where all the nets are solved simultaneously with the integration of via delays: (1) optimization of the total sum of net delays and reduction of slew violations; (2) minimization of critical path timing in selected nets.
For on-chip signal routing, the bundled bits in one group may have different
pin locations, but they have to be routed in a regular manner by sharing common topologies. Very few previous works target inter-bit regularity via multi-layer topology selection. Furthermore, the routability and wire-length of the signal bits should also be optimized. Then an advanced synergistic routing engine is promoted, which is able to not only control routability and wire-length but also guide each bit routing intelligently for design regularity.
For optical-electrical co-design routing, optical interconnect shows its
advantage due to the dominance of bandwidth-distance-power properties. The previous works lack a detailed exploration of optical-electrical co-design for on-chip interconnects. During the transmission, signal quality can be affected by various loss sources and Electrical to Optical (EO)/Optical to Electrical (OE) conversion overheads should also be considered. Then a power-efficient routing flow for on-chip signals is presented, where optical connections can collaborate with electrical wires seamlessly.
The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches are able to achieve the improvements regarding specific metrics and eventually benefit the routing flow.Electrical and Computer Engineerin
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