Error Containment in the Presence of Metastability

Error containment is an important concept in fault tolerant system design, and techniques like voting are applied to mask erroneous outputs, thus preventing their propagation. In this presentation we will use the example of DARTS, a fault-tolerant distributed clock generation scheme in hardware, to demonstrate that metastability is a substantial threat to error containment. We will illustrate how metastability can originate and propagate such that a single fault may upset the system. The main conclusion is that modeling efforts on all design levels are definitely required in order to mitigate and quantify the deteriorating effect of metastability on system dependability

08371 Abstracts Collection -- Fault-Tolerant Distributed Algorithms on VLSI Chips

From September the $7^{text{th}}$, 2008 to September the $10^{text{th}}$, 2008 the Dagstuhl Seminar 08371 ``Fault-Tolerant Distributed Algorithms on VLSI Chips \u27\u27 was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. The seminar was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of future-generation VLSI chips. During the seminar, several participants from both the VLSI and distributed algorithms\u27 discipline, presented their current research, and ongoing work and possibilities for collaboration were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

How to speedup fault-tolerant clock generation in VLSI systems-on-chip via pipelining

Fault-tolerant clocking schemes become inevitable when it comes to highly-reliable chip designs. Because of the additional hardware overhead, existing solutions are considerably slower than their non-reliable counterparts. In this paper, we demonstrate that pipelining is a viable approach to speed up the distributed fault-tolerant DARTS clock generation approach introduced in (Függer, Schmid, Fuchs, Kempf, EDCC'06), where a distributed Byzantine fault-tolerant tick generation algorithm has been used to replace the traditional quartz oscillator and highly balanced clock tree in VLSI Systems-on-Chip (SoCs). We provide a pipelined version of the original DARTS algorithm, termed pDARTS, together with a novel modeling and analysis framework for hardware-implemented asynchronous fault-tolerant distributed algorithms, which is employed for rigorously analyzing its correctness & performance. Our results, which have also been confirmed by the experimental evaluation of an FPGA prototype implementation, reveal that pipelining indeed allows to entirely remove the adverse effect of large interconnect delays on the achievable clock frequency, and demonstrate again that methods and results from distributed algorithms research can successfully be applied in the VLSI context

Fault-tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation

Today's hardware technology presents a new challenge in designing robust systems. Deep submicron VLSI technology introduced transient and permanent faults that were never considered in low-level system designs in the past. Still, robustness of that part of the system is crucial and needs to be guaranteed for any successful product. Distributed systems, on the other hand, have been dealing with similar issues for decades. However, neither the basic abstractions nor the complexity of contemporary fault-tolerant distributed algorithms match the peculiarities of hardware implementations. This paper is intended to be part of an attempt striving to overcome this gap between theory and practice for the clock synchronization problem. Solving this task sufficiently well will allow to build a very robust high-precision clocking system for hardware designs like systems-on-chips in critical applications. As our first building block, we describe and prove correct a novel Byzantine fault-tolerant self-stabilizing pulse synchronization protocol, which can be implemented using standard asynchronous digital logic. Despite the strict limitations introduced by hardware designs, it offers optimal resilience and smaller complexity than all existing protocols.Comment: 52 pages, 7 figures, extended abstract published at SSS 201

Design of robust asynchronous reconfigurable controllers for parallel synchronization using embedded graphs

PhD Thesis: This is a revised version received 24/5/16. The definitive version is the print copy in the Research Reserve Collection of the University LibrarySynchronization is a key System-on-Chip (SoC) design issue in modern technologies. As the number of operating points under consideration increases, specifications which are capable of altering key parameters such as the time available for synchronization and Mean Time Between Failures (MTBF) in response to input from the user/system become desirable. This thesis explores how a combination of parallelism and scheduling, referred to as wagging, can be utilized to construct schedulers for synchronizer designs which are capable of pooling the gain-bandwidth products of their composite devices, in order to satisfy this requirement. In this work, we explore the ways in which the areas of graph theory and reconfigurable hardware design can be applied to generate both combinational and sequential scheduler designs, which satisfy the behavior requirement above. Further to this point, this work illustrates that such a scheduler is primarily comprised of an interrupt subsystem, and a reconfigurable token ring. This thesis explores how both of these components can be controlled in absence of a clock signal, as well as the design challenges inherent to each part. The final noteworthy issue in this study is with regard to the flow control of data in a parallel synchronizer that incorporates a First-In First-Out (FIFO) buffer to decouple the reading and writing operations from each other. Such a structure incurs penalties if the data rates on both sides are not well matched. This work presents a method by which combinations of serial and parallel reading operations are used to minimize this mismatch

Energy-Efficient Digital Circuit Design using Threshold Logic Gates

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.Dissertation/ThesisDoctoral Dissertation Computer Science 201

Roadmap on commercialization of metal halide perovskite photovoltaics

Perovskite solar cells (PSCs) represent one of the most promising emerging photovoltaic technologies due to their high power conversion efficiency. However, despite the huge progress made not only in terms of the efficiency achieved, but also fundamental understanding of the relevant physics of the devices and issues which affect their efficiency and stability, there are still unresolved problems and obstacles on the path toward commercialization of this promising technology. In this roadmap, we aim to provide a concise and up to date summary of outstanding issues and challenges, and the progress made toward addressing these issues. While the format of this article is not meant to be a comprehensive review of the topic, it provides a collection of the viewpoints of the experts in the field, which covers a broad range of topics related to PSC commercialization, including those relevant for manufacturing (scaling up, different types of devices), operation and stability (various factors), and environmental issues (in particular the use of lead). We hope that the article will provide a useful resource for researchers in the field and that it will facilitate discussions and move forward toward addressing the outstanding challenges in this fast-developing field

Radiation hardness study of high purity silicon and the development of a radiation damage monitoring system for silicon devices in mixed radiation fields

This thesis describes an experimental study into the radiation hardness of high purity silicon. This material is principally used in the manufacture of silicon based microstrip detectors and other similar devices. Radiation detector test structures which had been fabricated on the base of different types of silicon were exposed to ~1 MeV neutrons. This was done to determine the role of different impurities in the formation of radiation induced crystallographic defects within the silicon lattice. Oxygenated silicon, nitrogenised silicon and silicon containing the standard residual impurities was investigated. The effect of the deep level states associated with the defects on the detector electrical properties was also studied. At the relatively high neutron fluence employed, up to 7.5x10(superscript 13) n.cm(superscript -2), the conventional capacitance based Deep Level Transient Spectroscopy (DLTS) technique is not applicable. In order to detect and measure the properties of the defects a new technique was used known as Optical Deep Level Transient Conductance Spectroscopy (ODLTCS). Spectral features identified in the ODLTCS spectra were attributed to known radiation induced defects in silicon through the comparison of the measured energy levels of the associated deep level states and the measured introduction rates with data contained in the literature. Using ODLTCS the kinetics of the growth and contraction of particular defect concentrations in each of the irradiated detector types was measured as a function of room temperature annealing. Correlation in the evolution of the radiation induced C(subscript i)-O(subscript i) and the short term annealing of the effective impurity concentration (N[subscript eff]) was observed. Based on this finding a microscopic explanation for the improved radiation hardness of oxygenated silicon is described. Other possible mechanisms of defect engineering were also investigated. No deep level defect identified from the ODLTCS spectra could be attributed to the long term reverse anneal of N(subscript eff). This suggested that the responsible defect had a energy state outside the ODLTCS detection limit of less than (0.16 eV) as measured from either the conduction or valence band edge. Significant reduction in the production rate of the V-O defect was observed in nitrogenised silicon. Evidence supporting possible metastability of the V-O defect was also obtained. Another important aspect of this research was the development of technologies for use in the on-line monitoring of radiation damage to silicon devices in mixed radiation fields. It is shown that a PIN Dosimeter diode which has been calibrated in an epithermal neutron beam in terms of (?, see abstract in 01Front file) can be used to measure (?, see abstract in 01Front file) in a fast neutron field. This finding supports the use of a PIN Dosimeter Diode for measuring (?, see abstract in 01Front file) in neutrons fields with any arbitrary energy spectra. The response of the PIN Dosimeter Diode in a high energy electron field in terms of (?, see abstract in 01Front file) is studied. Based on experimental findings it is reasoned that PIN Dosimeter Diode can provide a universal means of measuring dose associated with Non Ionising Energy Loss (NIEL) in silicon when exposed to any mixed radiation field in terms of (?, see abstract in 01Front file). Sensors for measuring does due to Ionising Energy Loss (IEL) in SiO(subscript 2) when exposed to mixed radiation fields were also investigated. It is shown that an IEL sensor based on photodetector is not suitable in a radiation environment containing NIEL type radiations. An alternative sensor in the form of MOSFET is found to suitably radiation hard against dose associated with NIEL and able to measure IEL over a wide range of response. Based on the MOSFET and PIN Dosimeter Diode results a Radiation Damage Monitoring System is designed for the measurement of damage to electronic devices in mixed radiation fields. The system was implemented in the Belle experiment at the KEK B-Factory in Japan, and within the lepton collider at SLAC in the USA

Methods to improve the reliability and resiliency of near/sub-threshold digital circuits

Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy required for computations by as much as 6 times. However, when operating at near/sub-threshold voltages (where the supply voltage is near or below the threshold of the transistors), imperfections in transistor manufacturing, changes in temperature, and other difficult-to-predict factors cause wide variations in the timing of Complementary Metal-Oxide Semiconductor (CMOS) circuits due to an increased sensitivity at lower voltages. These increased variations result in poor aggregate performance and cause increased rates of error occurrence in computation. This work introduces several new methods to improve the reliability of near/sub-threshold circuits. The first is a design automation technique that is used to aid in low-voltage digital standard cell synthesis. Second, two circuit-level techniques are also introduced that aim to improve the reliability and resiliency of digital circuits by means of completion/error detection. These techniques are shown to improve speed and lower energy consumption at low overheads compared to previous methods. Most importantly, these circuit-level methods are specifically designed to operate at low voltages and can themselves tolerate variations and operation in harsh environments. Finally, a test-chip prototype designed in 65nm-CMOS demonstrates the practicality and feasibility of a proposed current sensing error detector