Visual inspection : image sampling, algorithms and architectures

The thesis concerns the hexagonal sampling of images, the processing of industrially derived images, and the design of a novel processor element that can be assembled into pipelines to effect fast, economic and reliable processing. A hexagonally sampled two dimensional image can require 13.4% fewer sampling points than a square sampled equivalent. The grid symmetry results in simpler processing operators that compute more efficiently than square grid operators. Computation savings approaching 44% arc demonstrated. New hexagonal operators arc reported including a Gaussian smoothing filter, a binary thinner, and an edge detector with comparable accuracy to that of the Sobel detector. The design of hexagonal arrays of sensors is considered. Operators requiring small local areas of support are shown to be sufficient for processing controlled lighting and industrial images. Case studies show that small features in hexagonally processed images maintain their shape better, and that processes can tolerate a lower signal to noise ratio, than that for equivalent square processed images. The modelling of small defects in surfaces has been studied in depth. The flexible programmable processor element can perform the low level local operators required for industrial image processing on both square and hexagonal grids. The element has been specified and simulated by a high level computer program. A fast communication channel allows for dynamic reprogramming by a control computer, and the video rate element can be assembled into various pipeline architectures, that may eventually be adaptively controlled

System on fabrics utilising distributed computing

The main vision of wearable computing is to make electronic systems an important part of everyday clothing in the future which will serve as intelligent personal assistants. Wearable devices have the potential to be wearable computers and not mere input/output devices for the human body. The present thesis focuses on introducing a new wearable computing paradigm, where the processing elements are closely coupled with the sensors that are distributed using Instruction Systolic Array (ISA) architecture. The thesis describes a novel, multiple sensor, multiple processor system architecture prototype based on the Instruction Systolic Array paradigm for distributed computing on fabrics. The thesis introduces new programming model to implement the distributed computer on fabrics. The implementation of the concept has been validated using parallel algorithms. A real-time shape sensing and reconstruction application has been implemented on this architecture and has demonstrated a physical design for a wearable system based on the ISA concept constructed from off-the-shelf microcontrollers and sensors. Results demonstrate that the real time application executes on the prototype ISA implementation thus confirming the viability of the proposed architecture for fabric-resident computing devices

Implementation of a real time Hough transform using FPGA technology

This thesis is concerned with the modelling, design and implementation of efficient architectures for performing the Hough Transform (HT) on mega-pixel resolution real-time images using Field Programmable Gate Array (FPGA) technology. Although the HT has been around for many years and a number of algorithms have been developed it still remains a significant bottleneck in many image processing applications. Even though, the basic idea of the HT is to locate curves in an image that can be parameterized: e.g. straight lines, polynomials or circles, in a suitable parameter space, the research presented in this thesis will focus only on location of straight lines on binary images. The HT algorithm uses an accumulator array (accumulator bins) to detect the existence of a straight line on an image. As the image needs to be binarized, a novel generic synchronization circuit for windowing operations was designed to perform edge detection. An edge detection method of special interest, the canny method, is used and the design and implementation of it in hardware is achieved in this thesis. As each image pixel can be implemented independently, parallel processing can be performed. However, the main disadvantage of the HT is the large storage and computational requirements. This thesis presents new and state-of-the-art hardware implementations for the minimization of the computational cost, using the Hybrid-Logarithmic Number System (Hybrid-LNS) for calculating the HT for fixed bit-width architectures. It is shown that using the Hybrid-LNS the computational cost is minimized, while the precision of the HT algorithm is maintained. Advances in FPGA technology now make it possible to implement functions as the HT in reconfigurable fabrics. Methods for storing large arrays on FPGA’s are presented, where data from a 1024 x 1024 pixel camera at a rate of up to 25 frames per second are processed

An Intelligent Architecture Based on Field Programmable Gate Arrays Designed to Detect Moving Objects by Using Principal Component Analysis

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices

Energy efficient hardware acceleration of multimedia processing tools

The world of mobile devices is experiencing an ongoing trend of feature enhancement and generalpurpose multimedia platform convergence. This trend poses many grand challenges, the most pressing being their limited battery life as a consequence of delivering computationally demanding features. The envisaged mobile application features can be considered to be accelerated by a set of underpinning hardware blocks Based on the survey that this thesis presents on modem video compression standards and their associated enabling technologies, it is concluded that tight energy and throughput constraints can still be effectively tackled at algorithmic level in order to design re-usable optimised hardware acceleration cores. To prove these conclusions, the work m this thesis is focused on two of the basic enabling technologies that support mobile video applications, namely the Shape Adaptive Discrete Cosine Transform (SA-DCT) and its inverse, the SA-IDCT. The hardware architectures presented in this work have been designed with energy efficiency in mind. This goal is achieved by employing high level techniques such as redundant computation elimination, parallelism and low switching computation structures. Both architectures compare favourably against the relevant pnor art in the literature. The SA-DCT/IDCT technologies are instances of a more general computation - namely, both are Constant Matrix Multiplication (CMM) operations. Thus, this thesis also proposes an algorithm for the efficient hardware design of any general CMM-based enabling technology. The proposed algorithm leverages the effective solution search capability of genetic programming. A bonus feature of the proposed modelling approach is that it is further amenable to hardware acceleration. Another bonus feature is an early exit mechanism that achieves large search space reductions .Results show an improvement on state of the art algorithms with future potential for even greater savings

Kodizajn arhitekture i algoritama za lokalizacijumobilnih robota i detekciju prepreka baziranih namodelu

This thesis proposes SoPC (System on a Programmable Chip) architectures for efficient embedding of vison-based localization and obstacle detection tasks in a navigational pipeline on autonomous mobile robots. The obtained results are equivalent or better in comparison to state-ofthe- art. For localization, an efficient hardware architecture that supports EKF-SLAM's local map management with seven-dimensional landmarks in real time is developed. For obstacle detection a novel method of object recognition is proposed - detection by identification framework based on single detection window scale. This framework allows adequate algorithmic precision and execution speeds on embedded hardware platforms.Ova teza bavi se dizajnom SoPC (engl. System on a Programmable Chip) arhitektura i algoritama za efikasnu implementaciju zadataka lokalizacije i detekcije prepreka baziranih na viziji u kontekstu autonomne robotske navigacije. Za lokalizaciju, razvijena je efikasna računarska arhitektura za EKF-SLAM algoritam, koja podržava skladištenje i obradu sedmodimenzionalnih orijentira lokalne mape u realnom vremenu. Za detekciju prepreka je predložena nova metoda prepoznavanja objekata u slici putem prozora detekcije fiksne dimenzije, koja omogućava veću brzinu izvršavanja algoritma detekcije na namenskim računarskim platformama

Developing advanced mathematical models for detecting abnormalities in 2D/3D medical structures.

Detecting abnormalities in two-dimensional (2D) and three-dimensional (3D) medical structures is among the most interesting and challenging research areas in the medical imaging field. Obtaining the desired accurate automated quantification of abnormalities in medical structures is still very challenging. This is due to a large and constantly growing number of different objects of interest and associated abnormalities, large variations of their appearances and shapes in images, different medical imaging modalities, and associated changes of signal homogeneity and noise for each object. The main objective of this dissertation is to address these problems and to provide proper mathematical models and techniques that are capable of analyzing low and high resolution medical data and providing an accurate, automated analysis of the abnormalities in medical structures in terms of their area/volume, shape, and associated abnormal functionality. This dissertation presents different preliminary mathematical models and techniques that are applied in three case studies: (i) detecting abnormal tissue in the left ventricle (LV) wall of the heart from delayed contrast-enhanced cardiac magnetic resonance images (MRI), (ii) detecting local cardiac diseases based on estimating the functional strain metric from cardiac cine MRI, and (iii) identifying the abnormalities in the corpus callosum (CC) brain structure—the largest fiber bundle that connects the two hemispheres in the brain—for subjects that suffer from developmental brain disorders. For detecting the abnormal tissue in the heart, a graph-cut mathematical optimization model with a cost function that accounts for the object’s visual appearance and shape is used to segment the the inner cavity. The model is further integrated with a geometric model (i.e., a fast marching level set model) to segment the outer border of the myocardial wall (the LV). Then the abnormal tissue in the myocardium wall (also called dead tissue, pathological tissue, or infarct area) is identified based on a joint Markov-Gibbs random field (MGRF) model of the image and its region (segmentation) map that accounts for the pixel intensities and the spatial interactions between the pixels. Experiments with real in-vivo data and comparative results with ground truth (identified by a radiologist) and other approaches showed that the proposed framework can accurately detect the pathological tissue and can provide useful metrics for radiologists and clinicians. To estimate the strain from cardiac cine MRI, a novel method based on tracking the LV wall geometry is proposed. To achieve this goal, a partial differential equation (PDE) method is applied to track the LV wall points by solving the Laplace equation between the LV contours of each two successive image frames over the cardiac cycle. The main advantage of the proposed tracking method over traditional texture-based methods is its ability to track the movement and rotation of the LV wall based on tracking the geometric features of the inner, mid-, and outer walls of the LV. This overcomes noise sources that come from scanner and heart motion. To identify the abnormalities in the CC from brain MRI, the CCs are aligned using a rigid registration model and are segmented using a shape-appearance model. Then, they are mapped to a simple unified space for analysis. This work introduces a novel cylindrical mapping model, which is conformal (i.e., one to one transformation and bijective), that enables accurate 3D shape analysis of the CC in the cylindrical domain. The framework can detect abnormalities in all divisions of the CC (i.e., splenium, rostrum, genu and body). In addition, it offers a whole 3D analysis of the CC abnormalities instead of only area-based analysis as done by previous groups. The initial classification results based on the centerline length and CC thickness suggest that the proposed CC shape analysis is a promising supplement to the current techniques for diagnosing dyslexia. The proposed techniques in this dissertation have been successfully tested on complex synthetic and MR images and can be used to advantage in many of today’s clinical applications of computer-assisted medical diagnostics and intervention

Parallel and Distributed Computing

The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing