Thermal transport in thin films and across interfaces

Heat dissipation is a critical bottleneck for microelectronic device performance and longevity. At micrometer and nanometer length scales heat carriers scatter at the boundaries of the material reducing its thermal conductivity. Additionally, thermal boundary conductance across dissimilar material interfaces becomes a dominant factor due to the increase in surface area relative to the volume of device layers. Therefore, techniques for monitoring spatially varying temperature profiles, and methods to improve thermal performance are critical to future device design and optimization. The first half of this thesis focused on frequency domain thermoreflectance (FDTR) to measure thermal transport in nanometer-thick polymer films and across an organic-inorganic interface. Hybrid structures of organic and inorganic materials are widely used in devices such as batteries, solar cells, transistors, and flexible electronics. The Langmuir-Blodgett (LB) technique was used to fabricate nanometer-thick polymer films ranging from 2 - 30 nm. FDTR was then used to experimentally determine the thermal boundary conductance between the polymer and solid substrates. The second half of the thesis focused on developing a fundamental understanding of thermal transport in wide-bandgap (WBG) materials, such as GaN, and ultrawide-bandgap (UWBG) materials, such as diamond, to improve thermal dissipation in power electronic devices. Improvements in WBG materials and device technologies have slowed as thermal properties limit their performance. UWBG materials can provide a dramatic leap in power electronics technologies while temporarily sidestepping the problems associated with their WBG cousins. However, for power electronic devices based on WBG- and UWBG-materials to reach their full potential the thermal dissipation issues in these hard-driven devices must be understood and solved. FDTR provides a comprehensive pathway towards fully understanding the physics governing phonon transport in WBG- and UWBG-based devices. By leveraging FDTR imaging and measuring samples as a function of temperature, defect concentration, and thickness, in conjunction with transport models, a well-founded understanding of the dominant thermal-carrier scattering mechanisms in these devices was achieved. With this knowledge we developed pathways for their mitigation

Effects of edge roughness on optical scattering from periodic microstructures

Planar photonic crystals and other microstructured surfaces have important applications in a number of emerging technologies. However, these structures can be difficult to fabricate in a consistent manner. Rapid, precise measurements of critical parameters are needed to control the fabrication process, but current measurement techniques tend to be slow and often require that the sample be modified in order to make the measurement. Optical scattering can provide a rapid, non-destructive, and precise method for measuring these structures, and optical scatterometry is a good candidate technique for measuring micro-structured surfaces for process control. However, variations in the profile, such as those caused by edge roughness, can make significant contributions to the uncertainty in scatterometry measurements. Because of the multi- dimensional nature of the problem, modeling these variations can be computationally expensive. This dissertation examines the effects of edge roughness on optical scatterometry signals. Rigorous numerical simulations show that the effects of edge roughness are sensitive to the correlation length and the frequency content of the roughness as well as its amplitude. However, these rigorous calculations are computationally expensive. A less computationally expensive model based on a generalized Bruggeman effective medium approximation is developed and shown to be effective for modeling the effects of short correlation length edge roughness on optical scatterometry signals

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

Fabrication and nanoroughness characterization of specific nanostructures and nanodevice

Nanoroughness is becoming a very important specification for many nanostructures and nanodevices, and its metrology impacts not only the nanodevice properties of interest, but also its material selection and process development. This Ph.D. thesis presents an investigation into fabrication and nanoroughness characterization of nanoscale specimens and MIS (metal-insulator-semiconductor) capacitors with 2 HfO as a high k dielectric. Self-affine curves and Gaussian, non-Gaussian, self-affine as well as complicated rough surfaces were characterized and simulated. The effects of characteristic parameters on the CD (critical dimension) variation and the properties of these rough surfaces were visualized. Compared with experimental investigations, these simulations are flexible, low cost and highly efficient. Relevant conclusions were frequently employed in subsequent investigations. A proposal regarding the thicknesses of the deposited films represented by nominal linewidths and pitch was put forward. The MBE (Molecular Beam Epitaxy) process was introduced and AlGaAs and GaAs were selected to fabricate nanolinewidth and nanopitch specimens on GaAs substrate with nominal linewidths of 2nm, 4nm, 6nm and 8nm, and a nominal pitch of 5nm. HRTEM (High Resolution Transmission Electron Microscopy) image-based characterization of LER/LWR (Line Edge Roughness/Line Width Roughness) in real space and frequency domains demonstrated that the MBE-based process was capable of fabricating the desired nanolinewidth and nanopitch specimens and could be regulated accordingly. MIS capacitors with 2 HfO film as high k dielectric were fabricated, and SEM (Scanning Electron Microscope) image-based nanoroughness characterization, along with measurement of the MIS capacitor electrical properties were performed. It was concluded that the annealing temperature of the deposited 2 HfO film was an important process parameter and 700℃ was an optimal temperature to improve the properties of the MIS capacitor. Also, by quantitative characterization of the relevant nanoroughness, the fabrication process can be further regulated. The uncertainty propagation model of SEM based nanoroughness measurement was presented according to specific requirements of the relevant standards, ISO GPS (Geometric Product Specifications and Verification) and GUM (Guide to the Expression of Uncertainty in Measurement), and the method for implementating uncertainties was evaluated. The case study demonstrated that the total standard uncertainty of the nanoroughness measurement was 0.13nm, while its expanded uncertainty with the coverage factor k as 3 was 0.39nm. They are indispensable parts of LER/LWR measurement results

Stochastic Models of Surface Limited Electronic and Heat Transport in Metal and Semiconductor Contacts, Wires, and Sheets — Micro to Nano

We introduce novel statistical simulation approaches to include the e ect of surface roughness in coupled mechanical, electronic and thermal processes in N/MEMS and semiconductor devices in the 10 nm - 1 m range. A model is presented to estimate roughness rms and autocorrelation L from experimental surfaces and edges, and subsequently generate statistical series of rough geometrical devices from these observable parameters. Using such series of rough electrodes under Holm's theory, we present a novel simulation framework which predicts a contact resistance of 80 m in MEMS gold-gold micro-contacts, for applied pressures above 0.3 mN on 1 m 1 m surfaces. The non-contacting state of such devices is simulated through statistical Monte Carlo iterations on percolative networks to derive a time to electro-thermal failure through electrical discharges in the gas insulating metal electrodes. The observable parameters L and are further integrated in semi-classical solutions to the electronic and thermal Boltzman transport equation (BTE), and we show roughness limited heat and electronic transport in rough semiconductor nanowires and nano-ribbons. In this scope, we model for the rst time electrostatically con ned nanowires, where a reduction of electron - surface scattering leads to enhanced mobility in comparison to geometrical nanowires. In addition, we show extremely low thermal conductivity in Si, GaAs, and Ge nanowires down to 0.1 W/m/K for thin Ge wires with 56 nm width and = 3 nm. The dependency of thermal conductivity in (D= )2 leads to possible application in the eld of thermoelectric devices. For rough channels of width below 10 nm, electronic transport is additionally modeled using a novel non-parabolic 3D recursive Green function scheme, leading to an estimation of reduced electronic transmission in rough semiconductor wires based on the quantum nature of charge carriers. Electronic and thermal simulation schemes are nally extended to such 2D semiconductor materials as graphene, where low thermal conductivity is approximated below 1000 W/m/K for rough suspended graphene ribbons in accordance with recent experiments

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Energy Dissipation and Transport in Nanoscale Devices

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (~10^-8 W) to massive data centers (~10^9 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces