Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3

Strain-Reduction Induced Rise in Channel Temperature at Ohmic Contacts of GaN HEMTs

Operating temperature distributions in AlGaN/GaN gateless and gated devices are characterized and analyzed using the InfraScope temperature mapping system. For the first time, a substantial rise of channel temperature at the inner ends of ohmic contacts has been observed. Synchrotron radiation based high-resolution X-ray diffraction technique combined with drift -diffusion simulations show that strain reduction at the vicinity of ohmic contacts increases electric fi eld at these locations, resulting in the rise of lattice temperature. The thermal coupling of a high conductive tensile region at the contacts to a low conductive channel region is an origin of the temperature rise observed in both short- and long-channel gateless devices

Tuning of electrical properties in InAlN/GaN HFETs and Ba0.5Sr0.5TiO3/YIG Phase Shifters

Engineers know well from an early point in their training the trials and tribulations of having to make design tradeoffs in order to optimize one performance parameter for another. Discovering tradeoff conditions that result in the elimination of a loss associated with the enhancement of some other parameter (an improvement over a typical tradeoff), therefore, ushers in a new paradigm of design in which the constraints which are typical of the task at hand are alleviated. We call such a design paradigm “tuning” as opposed to “trading off”, and this is the central theme of this work. We investigate two types of microwave electronic devices, namely GaN-based heterostructure field effect transistors (HFETs) and tunable ferroelectric-ferrite-based microwave phase shifters. The “tuning” associated with these types of devices arises from the notion of an optimal 2DEG density, capable of achieving higher performance in terms of electron velocity and enhanced reliability in the case of the HFET, and the coupling of ferroelectric and ferrite materials in tunable microwave phase shifters, capable of achieving high differential phase shifts while at the same time mitigating the losses associated with impedance mismatching which typically arise when the phase is tuned. Promises and problems associated with HFET devices based on the intriguing InAlN/GaN material system will be described. We focus on the fundamental problem associated with the induction of the large density of carriers at the interface, namely the disintegration of an excess of longitudinal optical phonons (hot phonons) in the channel. We use microwave measurements in conjunction with stress tests to evidence the existence of an optimal 2DEG density wherein the hot phonon effect can be “tuned,” which allows for enhanced high frequency performance as well as device reliability. Next, we focus on the design, fabrication, and measurement of tunable phase shifters consisting of thin films of BaxSr1-xTiO3 (BST), which has the advantage of having high dielectric tunability as well as relatively low microwave loss. We discuss the design, fabrication, and measurement of a simple coplanar waveguide (CPW) type of phase shifter as well as a more complicated “hybrid” phase shifter consisting of a ferrite (YIG) in addition to BST. The use of such a bilayer allows one to “tune” the impedance of the phase shifters independently of the phase velocity through careful selection of the DC biasing magnetic fields, or alternatively through the use of an additional piezoelectric layer, bonded to YIG whose permeability can then be tuned through magnetostriction

Current collapse and device degradation in AlGaN/GaN heterostructure field effect transistors

A spectrum of phenomena related to the reliability of AlGaN/GaN HEMTs are investigated in this thesis using numerical simulations. The focus is on trap related phenomena that lead to decrease in the power output and failure of devices, i.e. the current collapse and the device degradation. The current collapse phenomenon has been largely suppressed using SiN passivation, but there are gaps in the understanding of the process leading to this effect. Device degradation, on the other side, is a pending problem of current devices and an obstacle to wide penetration of the market. Calibration of I-V measurements of two devices is performed with high accuracy to provide a trustworthy starting point for modelling the phenomena of interest. Traditionally, in simulations of nitride based HEMTs, only direct piezoelectric effect is taken into account and the resulting interface charge is thence independent of the electric field. In this work, the impact of the electric field via the converse piezoelectric effect is taken into account and its impact on the bound charge and the drain current is studied, as a refinement of the simulation methodology. It is widely believed that the current collapse is caused by a virtual gate, i.e. electrons leaked to the surface of the device. We have found a charge distribution that reproduced the I-V measurement that shows current collapse, hence validating the concept of the virtual gate. While it was previously shown that the virtual gate has a similar impact on the I-V curve as is observed during the current collapse, we believe that this is for the first time that a wide range of gate and drain voltages was calibrated. High gate/drain voltage leading to permanent degradation was also investigated. The hypothesis that stress induced defects and dislocations might be responsible for the degradation was tested but not fully confirmed. Finally, the leakage of electrons thought to be responsible for formation of the virtual gate and the current collapse due to the Poole-Frenkel emission, is simulated in order to explain the surface charge distribution responsible for the current collapse and deduced in Chapter 5

Reliability Characterisation of III-Nitrides Based Devices for Technology Development

III-nitrides based devices are considered as outstanding options for a range of extremely relevant applications. These devices can significantly improve the efficiency of high-power switching appliations. They are predicted to dominate applications in the low carbon economy. In recent years, these devices have been steadily improved and each year new record performances have been reported. Regardless of the superior performance of III-nitrides based devices, and particularly AlGaN/GaN high electron mobility transistors (HEMTs), achieving reliability at the same time as the high performance that the device boasts is a factor that is holding back widespread commercial and industrial development. Recoverable degradation (e.g. current collapse and on-resistance) and unrecoverable degradation (e.g. access resistance of contacts, and gate leakage current) persist to be limiting reliability factors. The mechanisms contributing towards performance and reliability degradation of AlGaN/GaN HEMTs, namely self-heating, charge trapping and strain, are required to be minimised; an important step before large-scale deployment can be attained. The strong coupling of these degradation mechanisms, under normal device operation, makes the quantitative contribution of each mechanism indistinct due to the lack of standard characterisation techniques. In this Thesis, the impact of the source/drain (S/D) and gate terminals of an AlGaN/GaN HEMT on its thermal management was investigated. Using Infrascope measurements, a substantial increase in temperature and resistance at the inner ends of the S/D contacts was observed. High-resolution X-ray diffraction technique combined with drift-diffusion (DD) simulations showed that strain reduction at the vicinity of S/D contacts is the origin of temperature rise. The strain reduction was also observed below the metal gate. Through electro-thermal simulations, the electrical stress on Ohmic contacts was shown to reduce the strain; leading to the inverse/converse piezoelectric effect. A new parametric technique was developed to decouple the mechanisms constituting device degradation in AlGaN/GaN HEMTs under normal device operation, namely self-heating and charge trapping. Both source (IS) and drain (ID) transient currents were used under various biasing conditions to analyse charge trapping behaviour. Two types of charge trapping mechanisms have been identified: (i) bulk trapping occurring on a time scale of 1 ms. Through monitoring the difference between I_S and I_D, bulk trapping time constant is shown to be independent of V_DS and V_GS. Also, V_GS is found to have no effect on the bulk trap density. Surface trapping is found to have a much greater impact on slow degradation when compared to self-heating and bulk trapping. At a short time scale (1ms), the dynamic ON resistance degradation is limited mainly by surface trapping accumulation and redistribution. Using the understanding of the degradation mechanism behaviour and origins, optimisations to the Ohmic and Schottky contacts as well as a new AlGaN/GaN HEMT architecture were proposed. In an attempt to improve the thermal management of S/D contacts, an Ohmic contact recess process is proposed to reduce the access resistance and enhance DC/RF performance of AlGaN/GaN HEMTs with a high Al concentration. A contact resistance (RC) of ~0.3 Ω.mm was achieved via optimal recess conditions. Small RC was found to lead to a higher current density at the inner edges of the contact, which resulted in a large increase of channel temperature beneath the S/D contacts. A highly n-doped AlGaN overgrowth layer was proposed to reduce the current density, and thus channel temperature at the Ohmic contacts. Titanium Nitride (TiN) Schottky processing was implemented to minimise the observed strain reduction beneath the gate metal. The optimal Schottky contact is obtained for TiN thicknesses of < 10 nm, which preserves the strain within the AlGaN barrier layer. As a result, Schottky barrier of 1.06 eV, a leakage current of 6 nA and improved linearity of 1.6 was achieved. In addition, C – V and I – V characterisations revealed very low trapping density within the optimised device. Lastly, a new device architecture was proposed to increase the 2-dimentional electron gas (2DEG) density and mobility, without compromising the enhancements of our proposed S/D and gate optimisations. This structure consists of (i) step-graded AlGaN barrier layer to increase strain and (ii) implementing AlN as the interfacial spacer layer

Simulation and Optimisation of SiGe MOSFETs

This research project is concerned with the development of methodology for simulating advanced SiGe MOSFETs using commercial simulators, the calibration of simulators against higher level Monte Carlo simulation results and real device measurements, and the application of simulation tools in the design of next generation p- channel devices. The methodology for the modelling and simulation of SiGe MOSFET devices is outlined. There are many simulation approaches widely used to simulate SiGe devices, such as Monte Carlo, hydrodynamic, energy transport, and drift diffusion. Different numerical techniques including finite difference, finite box and finite element methods, may be used in the simulators. The Si0.8Ge0.2 p-MOSFETs fabricated especially for high-field transport studies and the Si0.64Ge0.36 p-channel MOSFETs fabricated at Warwick and Southampton Universities with a CMOS compatible process in varying gate lengths were calibrated and investigated. Enhanced low field mobility in SiGe layers compared to Si control devices was observed. The results indicated that the potential of velocity overshoot effects for SiGe p-MOSFETs was considerably higher than Si counterparts, promising higher performance in the former at equal gate lengths at ultra-small devices. The effects of punchthrough stopper, undoped buffers and delta doping for SiGe p-MOSFETs were analysed systematically. It was found that the threshold voltage roll off might be reduced considerably by using an appropriate punchthrough stopper. In order to adjust the threshold voltage for digital CMOS applications, p-type delta doping was required for n+-polysilicon gate p-MOSFET. The use of delta doping made the threshold voltage roll off a more serious issue, therefore delta doping should be used with caution. The two-dimensional process simulator TSUPREM-4 and the two-dimensional device simulator MEDICI were employed to optimise and design Si/SiGe hybrid CMOS. The output of TSUPREM-4 was transferred automatically to the MEDICI device simulator. This made the simulation results more realistic. For devices at small gate length, lightly doped drain (LDD) structures were required. They would decrease the lateral subdiffusion and allow threshold voltage roll off to be minimised. These structures, however, would generally reduce drain current due to an increase in the series resistance of the drain region. Further consideration must be made of these trade-offs. Comparison between drift diffusion and hydrodynamic simulation results for SiGe p-MOSFETs were presented for the first time, with transport parameters extracted from our in-house full-band hole Monte Carlo transport simulator. It was shown that while drift diffusion and hydrodynamic simulations provided a reasonable estimation of the I-V characteristics for Si devices, the same could not be said for aggressively scaled SiGe devices. The resulting high fields at the source end of the devices meant that nonequilibrium transport effects were significant. Therefore for holes, models based on an isotropic carrier temperature were no longer appropriate, as it was shown by analysing the tensor components of the carrier temperature obtained from Monte Carlo simulation. Two-dimensional drift diffusion and Monte Carlo simulations of well-tempered Si p-MOSFETs with gate lengths of 25 and 50 nm were performed. By comparing Monte Carlo simulations with carefully calibrated drift diffusion results, it was found that nonequilibrium transport was important for understanding the high current device characteristics in sub 0.1 mum p-MOSFETs. The well-tempered devices showed better characteristics than the conventional SiGe devices. Both threshold voltage roll off and the subthreshold slope were acceptable although the effective channel length of this device was reduced from 50 nm to 25 nm. In order to adjust the threshold voltage for the digital CMOS applications, p-type delta doping was used for 50 nm well-tempered SiGe p- MOSFETs. As the delta doping made the threshold voltage roll off too serious, it was not suitable for 25 nm well-tempered SiGe p-MOSFETs

AlGaN/GaN Dual Channel HFETs and Realization of GaN Devices on different substrates

GaN-based HFETs demonstrate ubiquitous high power and high frequency performance and attract tremendous research efforts. Even though significant advances have been achieved, there still exist some critical issues needed to be investigated and solved. In particular, high defect densities due to inhomogeneous growth and operation under high power conditions bring many unique problems which are not so critical in the conventional Si and GaAs materials systems. In order to reduce the defect density and heat dissipation of GaN-based HFETs, research work on the realization of GaN-based HFETs on bulk GaN substrate has been carried out and the key problems have been identified and solved. Hot phonon scattering is the bottleneck which limits the enhancement of electron velocity in the GaN 2DEG channel. It is found that the plasmon-phonon coupling is the mechanism for converting of hot phonons into high group velocity acoustic phonons. In order to push more electrons into the GaN 2DEG channel in the plasmon-phonon coupling regime and to further reduce the hot phonon lifetime, a novel AlGaN/GaN dual channel HFET structure has been proposed. The growth, fabrication and characterization of such a AlGaN/GaN dual channel HFET structure has been carried out. Conventionally GaN-based light emitting diodes and laser diodes are grown and fabricated using the c-plane III-nitride expitaxy layers. In c-plane III-nitride epi-layers, the polarization-induced electric field introduces spatial separation of electron and hole wave functions in quantum wells (QW)s used LEDs and laser diodes LDs and degrades quantum efficiency. As well, blueshift in the emission wavelength becomes inevitable with increasing injection current unless very thin QWs are employed. The use of nonpolar orientations, namely, m-plane or a-plane GaN, would solve this problem. So far, m-plane GaN has been obtained on LiAlO2 (100), m-plane SiC substrates, and m-plane bulk GaN, which all have limited availability and/or high cost. Silicon substrates are very attractive for the growth of GaN due to their high quality, good thermal conductivity, low cost, availability in large size, and ease with which they can be selectively removed before packaging for better light extraction and heat transfer when needed To realize the low cost and improve the internal quantum efficiency of GaN based light emitting diodes, the process for m-plane GaN growth on Si (112) substrates has been studied and optimized. The continuous m-plane GaN film is successfully grown on Si (112) substrates

GaN heterojunction FET device Fabrication, Characterization and Modeling

This dissertation is focused on the research efforts to develop the growth, processing, and modeling technologies for GaN-based Heterojunction Field Effect Transistors (HFETs). The interest in investigating GaN HFETs is motivated by the advantageous material properties of nitride semiconductor such as large band gap, large breakdown voltage, and high saturation velocity, which make it very promising for the high power and microwave applications. Although enormous progress has been made on GaN transistors in the past decades, the technologies for nitride transistors are still not mature, especially concerning the reliability and stability of the device. In order to improve the device performance, we first optimized the growth and fabrication procedures for the conventional AlGaN barrier HFET, on which high carrier mobility and sheet density were achieved. Second, the AlInN barrier HFET was successfully processed, with which we obtained improved I-V characteristics compared with conventional structure. The lattice-matched AlInN barrier is beneficial in the removal of strain, which leads to better carrier transport characteristics. Furthermore, new device structures have been examined, including recess-gate HFET with n+ GaN cap layer and gate-on-insulator HFET, among which the insertion of gate dielectrics helps to leverage both DC and microwave performances. In order to depict the microwave behavior of the HFET, small signal modeling approaches were used to extract the extrinsic and intrinsic parameters of the device. An 18-element equivalent circuit model for GaN HFET has been proposed, from which various extraction methods have been tested. Combining the advantages from the cold-FET measurements and hot-FET optimizations, a hybrid extraction method has been developed, in which the parasitic capacitances were attained from the cold pinch-off measurements while the rest of the parameters from the optimization routine. Small simulation error can be achieved by this method over various bias conditions, demonstrating its capability for the circuit level design applications for GaN HFET. Device physics modeling, on the other hand, can help us to reveal the underlying physics for the device to operate. With the development of quantum drift-diffusion modeling, the self-consistent solution to the Schrödinger-Poisson equations and carrier transport equations were fulfilled. Lots of useful information such as band diagram, potential profile, and carrier distribution can be retrieved. The calculated results were validated with experiments, especially on the AlInN layer structures after considering the influence from the parasitic Ga-rich layer on top of the spacer. Two dimensional cross-section simulation shows that the peak of electrical field locates at the gate edge towards the drain, and of different kinds of structures the device with gate field-plate was found to efficiently reduce the possibility of breakdown failure