681 research outputs found
Formal Verification of Abstract SystemC Models
In this paper we present a formal verification approach for abstract SystemC models. The approach allows checking expressive properties and lifts induction known from bounded model checking to a higher level, to cope with the large state space of abstract SystemC programs. The technique is tightly integrated with our SystemC to C transformation and generation of monitoring logic to form a complete and efficient method. Properties specifying both hardware and software aspects, e.g. pre- and post-conditions as well as temporal relations of transactions and events, can be specified. As shown by experiments modern proof techniques allow verifying important non-trivial behavior. Moreover, our inductive technique gives significant speed-ups in comparison to simple methods
Formal Verification of Probabilistic SystemC Models with Statistical Model Checking
Transaction-level modeling with SystemC has been very successful in
describing the behavior of embedded systems by providing high-level executable
models, in which many of them have inherent probabilistic behaviors, e.g.,
random data and unreliable components. It thus is crucial to have both
quantitative and qualitative analysis of the probabilities of system
properties. Such analysis can be conducted by constructing a formal model of
the system under verification and using Probabilistic Model Checking (PMC).
However, this method is infeasible for large systems, due to the state space
explosion. In this article, we demonstrate the successful use of Statistical
Model Checking (SMC) to carry out such analysis directly from large SystemC
models and allow designers to express a wide range of useful properties. The
first contribution of this work is a framework to verify properties expressed
in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and
probabilistic characteristics. Second, the framework allows users to expose a
rich set of user-code primitives as atomic propositions in BLTL. Moreover,
users can define their own fine-grained time resolution rather than the
boundary of clock cycles in the SystemC simulation. The third contribution is
an implementation of a statistical model checker. It contains an automatic
monitor generation for producing execution traces of the
model-under-verification (MUV), the mechanism for automatically instrumenting
the MUV, and the interaction with statistical model checking algorithms.Comment: Journal of Software: Evolution and Process. Wiley, 2017. arXiv admin
note: substantial text overlap with arXiv:1507.0818
Dependability Analysis of Control Systems using SystemC and Statistical Model Checking
Stochastic Petri nets are commonly used for modeling distributed systems in
order to study their performance and dependability. This paper proposes a
realization of stochastic Petri nets in SystemC for modeling large embedded
control systems. Then statistical model checking is used to analyze the
dependability of the constructed model. Our verification framework allows users
to express a wide range of useful properties to be verified which is
illustrated through a case study
Optimized Temporal Monitors for SystemC
SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation and identify a combination of settings that offers the best performance in terms of runtime overhead
Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing
Nowadays, demands for high performance keep on increasing in the wireless
communication domain. This leads to a consistent rise of the complexity and
designing such systems has become a challenging task. In this context, energy
efficiency is considered as a key topic, especially for embedded systems in
which design space is often very constrained. In this paper, a fast and
accurate power estimation approach for FPGA-based hardware systems is applied
to a typical wireless communication system. It aims at providing power
estimates of complete systems prior to their implementations. This is made
possible by using a dedicated library of high-level models that are
representative of hardware IPs. Based on high-level simulations, design space
exploration is made a lot faster and easier. The definition of a scenario and
the monitoring of IP's time-activities facilitate the comparison of several
domain-specific systems. The proposed approach and its benefits are
demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201
Dynamic Verification of SystemC with Statistical Model Checking
Many embedded and real-time systems have a inherent probabilistic behaviour
(sensors data, unreliable hardware,...). In that context, it is crucial to
evaluate system properties such as "the probability that a particular hardware
fails". Such properties can be evaluated by using probabilistic model checking.
However, this technique fails on models representing realistic embedded and
real-time systems because of the state space explosion. To overcome this
problem, we propose a verification framework based on Statistical Model
Checking. Our framework is able to evaluate probabilistic and temporal
properties on large systems modelled in SystemC, a standard system-level
modelling language. It is fully implemented as an extension of the Plasma-lab
statistical model checker. We illustrate our approach on a multi-lift system
case study
Embedded real-time monitoring using SystemC in IMA network
Avionics is one kind of domain where prevention prevails. Nonetheless fails
occur. Sometimes due to pilot misreacting, flooded in information. Sometimes
information itself would be better verified than trusted. To avoid some kind of
failure, it has been thought to add,in midst of the ARINC664 aircraft data
network, a new kind of monitoring
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
The increasing processing power of today’s HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
The increasing processing power of today’s HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).The work leading to these results has received funding from the European Community’s Seventh Framework Programme FP7/2007-2011 under grant agreement no. 611146
A SystemC-based Platform for Assertion-based Verification and Mutation Analysis in Systems Biology
Boolean models are gaining an increasing interest for reproducing dynamic behaviours, understanding processes, and predicting emerging properties of cellular signalling networks through in-silico experiments. They are emerging as avalid alternative to the quantitative approaches (i.e., based on ordinary differential equations) for exploratory modelling when little is known about reaction kinetics or equilibrium constants in the context of gene expression or signalling. Even though several approaches and software have been recently proposed for logic modelling of biological systems, they are limited to specific modelling contexts and they lack of automation in analysing biological properties such as complex attractors, molecule vulnerability, dose response. This paper presents a design and verification platform based on SystemC that applies methodologies and tools well established in the electronic-design automation (EDA) fieldsuch as assertion-based verification (ABV) and mutation analysis, which allow complex attractors (i.e., protein oscillations) and robustness/sensitivity of the signalling networks to be simulated and analysed. The paper reports the results obtained by applying such verification techniques for the analysis of the intracellular signalling network controlling integrin activation mediating leukocyte recruitment from the blood into the tissues
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