A Parameterization Scheme for Lossy Transmission Line Macromodels with Application to High Speed Interconnects in Mobile Devices

We introduce a novel parameterization scheme based on the generalized method of characteristics (MoC) formacromodels of transmission-line structures having a cross section depending on several free geometrical and material parameters. This situation is common in early design stages, when the physical structures still have to be finalized and optimized under signal integrity and electromagnetic compatibility constraints. The topology of the adopted line macromodels has been demonstrated to guarantee excellent accuracy and efficiency. The key factors are propagation delay extraction and rational approximations, which intrinsically lead to a SPICE-compatible macromodel stamp. We introduce a scheme that parameterizes this stamp as a function of geometrical and material parameters such as conductor-width and separation, dielectric thickness, and permettivity. The parameterization is performed via multidimensional interpolation of the residue matrices in the rational approximation of characteristic admittance and propagation operators. A significant advantage of this approach consists of the possibility of efficiently utilizing the MoC methodology in an optimization scheme and eventually helping the design of interconnects.We apply the proposed scheme to flexible printed interconnects that are typically found in portable devices having moving parts. Several validations demonstrate the effectiveness of the approac

Parametric macromodeling of lossy and dispersive multiconductor transmission lines

We propose an innovative parametric macromodeling technique for lossy and dispersive multiconductor transmission lines (MTLs) that can be used for interconnect modeling. It is based on a recently developed method for the analysis of lossy and dispersive MTLs extended by using the multivariate orthonormal vector fitting (MOVF) technique to build parametric macromodels in a rational form. They take into account design parameters, such as geometrical layout or substrate features, in addition to frequency. The presented technique is suited to generate state-space models and synthesize equivalent circuits, which can be easily embedded into conventional SPICE-like solvers. Parametric macromodels allow to perform design space exploration, design optimization, and sensitivity analysis efficiently. Numerical examples validate the proposed approach in both frequency and time domain

Incentives for Transmission Investment in the PJM Electricity Market: FTRs or Regulation (or Both?)

This paper presents an application of a mechanism that provides incentives to promote transmission network expansion in the area of the US electric system known as PJM. The applied mechanism combines the merchant and regulatory approaches to attract investment into transmission grids. It is based on rebalancing a two-part tariff in the framework of a wholesale electricity market with locational pricing. The expansion of the network is carried out through the sale of financial transmission rights for the congested lines. The mechanism is tested for 14-node and 17-node geographical coverage areas of PJM. Under Laspeyres weights, it is shown that prices converge to the marginal cost of generation, the congestion rent decreases, and the total social welfare increases. The mechanism is shown to adjust prices effectively given either non-peak or peak demand.Electricity transmission expansion, incentive regulation, PJM

Every Moment Counts: Synchrophasors for Distribution Networks with Variable Resources

Chapter 34 in the textbook, "Renewable Energy Integration: Practical Management of Variability, Uncertainty and Flexibility

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Guaranteed passive parameterized model order reduction of the partial element equivalent circuit (PEEC) method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach

Delay Extraction Based Equivalent Elmore Model For RLC On-Chip Interconnects

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed form solution models for signal integrity analysis of on-chip interconnects. The proposed model uses a delay extraction algorithm to improve the accuracy of two-pole Elmore based models used in the analysis of on-chip distributed RLC interconnects. In the proposed scheme, the time of fight signal delay is extracted without increasing the number of poles or affecting the stability of the transfer function. This algorithm is used for both unit step and ramp inputs. From the delay rational approximation of the transfer function, analytic fitted expressions are obtained for the 50% delay and rise time for unit step input. The proposed algorithm is tested on point to point interconnections and tree structure networks. Numerical examples illustrate improved 50% delay and rise time estimates when compared to traditional Elmore based two-pole models