Design of a process monitor and of peripheral circuits enabling the characterisation of CMOS 45nm Ultra Low Power and Litho Friendly optimised standard cells

L’evoluzione della tecnologia CMOS è caratterizzata dallo scaling delle dimensioni dei dispositivi e dalla riduzione del consumo di potenza. Dal momento che le difficoltà di realizzazione aumentano al diminuire delle dimensioni, nei nodi tecnologici più recenti la velocità del processo di scaling sta diminuendo. Uno dei maggiori problemi causati dalla riduzione delle dimensioni dei dispositivi è la variabilità del processo di fabbricazione. L’obiettivo di questo progetto è quello di ridurre gli effetti che la variabilità del processo di realizzazione nel nodo tecnologico CMOS 45 nm ha sulle prestazioni della logica digitale, grazie a metodi di design non convenzionali. In questo progetto è stato realizzato un testchip per studiare e quantificare i vantaggi, in termini di prestazioni, ottenuti tramite la progettazione di librerie standard-like ottimizzate secondo canoni di litho-friendliness (LF) e ultra low power (ULP). Le standard cells LF utilizzano layout estremamente regolari. Le standard cells ULP sono progettate per operare con tensioni di alimentazioni notevolmente ridotte. Il fine principale del testchip sta nell’ottenere una panoramica della variabilità locale e globale di parametri significativi nella progettazione digitale: ad esempio la frequenza di lavoro e il consumo di potenza. Inoltre, nel testchip sono stati realizzati alcuni circuiti originali per il monitoraggio della qualità del processo di fabbricazione. The evolution of the CMOS technology is characterized by the scaling of transistors size and by the reduction of their power dissipation. In the last technology nodes the speed of the scaling process is decreasing, since the complexity of the technology increases with its size reduction. One of the main issues caused by the shrinking of the transistor size is the variability of the fabrication process. The target of this project is to reduce the effects of the variability of the realisation process in a CMOS 45 nm technology node in digital circuits performances, using unconventional design methods. A testchip is realised in this project to investigate and to quantify the improvement of the circuit performances obtained through the design of dedicated litho-friendly (LF) and of the Ultra Low Power (ULP) standard-like libraries. The LF standard cells libraries are optimised for lithography using ultra regular layout styles. The ULP standard cells library is optimised to operate at extremely low supply voltage. The main aim of the testchip is to get insight into the local and the global variability of relevant parameters for digital design, such as operating frequency and power consumption. In this testchip some structures are also included, to develop some innovative circuits that should help to monitor the quality of the technology process

Low-power CMOS circuit design for fast infrared imagers

La present tesi de màster detalla novedoses tècniques circuitals per al disseny de circuits integrats digitals CMOS de lectura compactes, de baixa potència i completament programables, destinats a aplicacions d'IR d'alta velocitat operant a temperatura ambient. En aquest sentit, el treball recull i amplia notablement la recerca iniciada en el Projecte Final de Carrera "Tècniques de disseny CMOS per a sistemes de visió híbrids de pla focal modular" obtenint-se resultats específics en tres diferents àrees: Recerca de l'arquitectura òptima d'FPA, des del punt de vista funcional i de construcció física. Disseny d'un conjunt complet de blocs bàsics d'autopolarització, compensació de la capacitat d'entrada i del corrent d'obscuritat, conversió A/D i interfície d'E/S exclusivament digital, amb compensació de l'FPN. Aplicació industrial real: Integraciió de tres versions diferents de píxel per sensors PbSe d'IR i fabricació de mòduls ROIC monolítics i híbrids en tecnologia CMOS estàndard 0.35&·956;m 2-PoliSi4-metall. Caracterització elèctrica i òptica-preliminar de les llibreries de disseny

ULTRA ENERGY-EFFICIENT SUB-/NEAR-THRESHOLD COMPUTING: PLATFORM AND METHODOLOGY

Ph.DDOCTOR OF PHILOSOPH

Integrated Circuit Design for Miniaturized, Trackable, Ultrasound Based Biomedical Implants

This thesis focuses on the design of an ultrasonography compatible implantable sensor platform, as a novel approach that implements a miniaturized, battery-less, real-time trackable parallel biosensing system. In addition to the frontend circuit, a sub-nW fully integrated pH sensor is designed in a way that can be easily integrated with the proposed sonography-compatible sensor platform. Combining the two integrated circuits together, the whole system will be able to map in vivo physiological information acquired from a distributed set of sensors on top of the ultrasound movie, leading to the idea envisioned as “augmented ultrasonography”. Implemented in a 0.18 μm technology, an ultrasound power and data frontend circuit is designed to enable medical sensing implants to operate in an ultrasonography compatible way. When placed within the field of view of an imaging transducer, the frontend circuit harvests the power through a piece of piezo crystal from a minimally modified brightness-mode (B-mode) ultrasound imaging process that is commonly adopted in modern medical practices. The implant can also establish bi-directional data communication channels with the imaging transducer, allowing data to be transmitted in a way synchronized to the frame rate of the B-mode film. The design of the circuit is made possible by a combination of ultra-low-power circuit techniques and novel frontend circuit topologies, as imaging ultrasound waves in the form of short pulses with extremely low duty cycle poses challenges that has not previously seen in other implantable sensor systems. The proposed prototype achieves a total area of 0.6mm² for the integrated circuit (IC), as well as 71mm theoretical maximum implantable depth (up to 40 mm is verified experimentally). These two together give opportunities for this design to become the next generation solution for deep-tissue bio-sensing implants. Realized using the same 0.18 μm technology, the fully integrated pH sensor is designed to deliver accurate pH readouts, at a reasonable speed of 1 sample per second, while consuming only 0.72 nW of power. Using an ion-sensitive field effect transistor (ISFET) and reference field effect transistor pair (REFET), the IC requires minimum additional post fabrication to deliver 10-bit resolution pH readouts at an end-to-end sensitivity of 65.8 LSB/pH. When working as a standalone device, this work advances the state-of-the-art of ISFET based pH sensor design. With an addition of 0.46 mm² of area, it is possible to integrate it with the ultrasound sonography compatible implant platform. This potential integration will further advance the vision of the augmented ultrasonography: real-time display of physiological information in a B-mode film, with the help from a distributed bio-sensor system for deep-tissue physiology monitoring

Schottky Field Effect Transistors and Schottky CMOS Circuitry

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a bulk switching SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an increase in current injection with minimal process complexity. The different switching mechanism realized with this technique also reduces the ambipolar leakage current that has so often plagued SFETs of more conventional design. In addition, these devices have been utilized in a patent pending approach that may facilitate an increase in circuit density for devices of a given size. In other words, for example, it may be possible to achieve circuit density equivalent to 65 nm technology using a 90 nm process, while at the same time preserving or reducing local interconnect density for enhanced overall system speed. Fabrication details and electrical results will be discussed, as well as some initial modeling efforts toward gaining insight into the details of current injection at the metal-semiconductor (M-S) interface. The challenges faced using the ITS approach at aggressive scales will be discussed, as will the potential advantages and disadvantages of other approaches to SFET technology

Tri-band CMOS Circuit Dedicated for Ambient RF Energy Harvesting

RÉSUMÉ L'utilisation de systèmes sans fil connait une croissance rapide dans divers domaines tels que les réseaux de téléphonie cellulaire, Wi-Fi, Wi-Max, la radiodiffusion et les communications par satellite. Cette croissance mènera à une quantité considérable d'énergie électromagnétique générée dans l'air ambiant, mais toujours en dessous des limites de sécurité internationales. Ainsi, la recherche au niveau des systèmes de récupération d'énergie RF pour alimenter des appareils électroniques miniaturisés à faible consommation de puissance devient attrayante et prometteuse. Le bloc principal dans un système de récupération d'énergie RF est le redresseur qui détermine l'efficacité et la sensibilité de l'ensemble du système. Étant donné que la puissance RF ambiante est très faible, la quantité d'énergie captée par l'antenne l’est également. En outre, il y a des pertes au niveau du réseau d'adaptation d’impédance qui réduisent encore plus la puissance transmise au bloc redresseur. Par conséquent, la puissance disponible est trop faible pour faire fonctionner des redresseurs classiques. Dans ce mémoire, nous proposons trois redresseurs à trois-étages et à grilles totalement croisées-couplées en utilisant des transistors à faible tension de seuil afin d’opérer à de faibles puissances d'entrée. Les trois redresseurs ont été conçus et intégrés au sein d’une même puce fabriquée en utilisant une technologie CMOS 130nm d’IBM. Ils ont été optimisés à des fréquences de 880MHz, 1960MHz et 2.45GHz respectivement. Les résultats expérimentaux démontrent qu’ils atteignent une efficacité de conversion de puissance maximale de 62%, 62% et 56.2% respectivement. Les mesures montrent également une grande amélioration de l'efficacité à de faibles niveaux de puissance d'entrée. Afin de récupérer l'énergie ambiante de trois principales sources RF au Canada – GSM-850, GSM-1900 et Wi-Fi, un système de redresseur utilisé pour la combinaison de la puissance de ces trois canaux est simulé et analysé. Le système utilise une topologie consistant simplement à connecter les sorties des redresseurs ensemble pour charger le condensateur de charge. En dépit de la grande amélioration de l'efficacité et de la sensibilité dans la plage de 0-5μW, une baisse d'efficacité indésirable se produit aux puissances plus élevées. Ainsi, un nouveau bloc de gestion de l'alimentation est proposé. De plus, une antenne tri-bande est conçue et simulée pour diminuer le volume de l'ensemble du système de récupération d'énergie RF. En particulier, les pertes par réflexion obtenues sont de -25.43dB, -13.92dB et -12.73dB aux fréquences citées plus haut respectivement.---------- ABSTRACT Nowadays, the use of wireless systems has grown rapidly in various domains such as cellular phone networks, Wi-Fi, Wi-Max, radio broadcasting and satellite communications. The growing use of these wireless systems leads to considerable amount of electromagnetic energy generated in ambient air (of course, still below international safety limits). Thus the research in ambient RF energy harvesting system dedicated for powering up low-power-consumption miniaturized electronic devices becomes attractive and promising. The main block in a RF harvesting system is the rectifier which determines the efficiency and sensitivity of the whole system. Since ambient RF power is very low, the amount of power captured by the antenna is extremely low. Besides, there is loss on matching networks, thus the available power given to the rectifier block is too low for traditional rectifiers to operate. Therefore, in this master thesis, three three-stage fully gate cross-coupled rectifiers using low-thresholdvoltage transistors are proposed to overcome the dead zone in low input power range. The three rectifiers optimized at 880MHz, 1960MHz and 2.45GHz frequencies respectively are designed on one chip layout. Their experimental results are retrieved from this custom fabricated integrated circuit using IBM 130nm CMOS technology. They achieve peak efficiencies of 62%, 62% and 56.2% respectively and show great improvements on power conversion efficiency at low input power level. In order to harvest ambient RF energy from the three main RF contributors in Canada – GSM-850, GSM-1900 and Wi-Fi 2.4GHz, a rectifier system used for power combination from these three channels is simulated and analyzed. The system employs a simple topology by connecting the outputs together to charge the load capacitor. In spite of its high improvements on efficiency and sensitivity in 0-5μW range, an undesirable efficiency drop happens at higher input power levels. Thus an idea of power management block is proposed. In addition, a tri-band antenna is designed and simulated so as to decrease the volume of the overall RF energy harvesting system. It achieves return loss of -25.43dB, -13.92dB and - 12.73dB at each desired band respectively

Portable High Throughput Digital Microfluidics and On-Chip Bacteria Cultures

An intelligent, portable, and high throughput digital microfluidic (DMF) system is developed. Chapter 1 introduces microfluidics and DMF systems. In Chapter 2, a low-cost and high resolution capacitive-to-digital converter integrated circuit is used for droplet position detection. A field-programmable gate array FPGA is used as the integrated logic hub of the system for highly reliable and efficient control of the circuit. In this chapter a fast-fabricating PCB (printed circuit board) substrate microfluidic system is proposed. Smaller actuation threshold voltages than those previously reported are obtained. Droplets (3 µL) are actuated using 200 V, 500 Hz DC pulses. Droplet positions can be detected and displayed on a PC-based 3D animation in real time. The actuators and the capacitance sensing circuits are implemented on one PCB to reduce the size of the system. In Chapter 3, an intelligent EWOD (electrowetting on dielectric) top plate control system is proposed. The dynamic top plate is controlled by a piezoelectric (PZT) cantilever structure. A high resolution laser displacement sensor is used to monitor the deflection of the top plate. The gap height optimization and the harmonic vibration significantly improve the droplet velocity and decrease the droplet minimum threshold actuation voltage. The top plate vibration induced actuation improvement is magnitude and frequency dependent. 100 µm and 200 µm vibrations are tested at 25 Hz. Vibration frequencies at 5 Hz, 10 Hz, and 20 Hz are tested while the magnitude is 200 µm. Results show greater improvements are achieved at larger vibration magnitudes and higher vibration frequencies. With a vibrated top plate, the largest reduction of the actuation voltage is 76 VRMS for a 2.0 µl DI water droplet. The maximum droplet instantaneous velocity is around 9.3 mm/s, which is almost 3 times faster than the droplet velocity without top plate vibration. Liquid that has different hysteresis such as acetonitrile with various concentrations are used as a control to show its compatibility with the proposed DMF chip. Contact line depinning under top plate vibration is observed, which indicates the underlying mechanism for the improvements in actuation velocity and threshold voltage. The top plate control technique reported in this study makes EWOD DMF chips more reliable for point of care diagnostics. In Chapter 4, the mechanisms of the improvements were investigated by observing the detailed changes in the contact angle hysteresis using both parallel and nonparallel top plates. In Chapter 5, on-chip cell cultures are used for anti-biotic resistant bacteria detection. The passively dispensed on-chip cell cultures realize the isolated micro environment electrochemistry measurement, shorten the culturing time, and reduce the required sample volume. The design of the next generation ultra-portable DMF system is covered in the Appendix. Detailed technical notes and hardware design is covered in the Appendix. The proposed portable and high throughput DMF system with on-chip cell cultures have a great potential to change the standards for micro-environment culturing technologies, which will significantly improve the efficiency of actuation, sensing, and detecting performance of the DMF systems

Simulation and implementation of novel deep learning hardware architectures for resource constrained devices

Corey Lammie designed mixed signal memristive-complementary metal–oxide–semiconductor (CMOS) and field programmable gate arrays (FPGA) hardware architectures, which were used to reduce the power and resource requirements of Deep Learning (DL) systems; both during inference and training. Disruptive design methodologies, such as those explored in this thesis, can be used to facilitate the design of next-generation DL systems

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations