A fast-acting protection scheme for series compensators in a medium-voltage network

In recent 20 years medium voltage networks have been becoming one of the important interfaces between the power plants and loads due to the increasing load demand as well as number of distributed generators connected to the network. This is the reason, managing the power flow, and voltage profile of the network at the lowest possible power losses and also price are of the utmost importance. The series compensators such as a static synchronous series compensator are of the most cost effective power compensators that also have the high efficiency in controlling the power flow and voltage profile. However, their drawback is their vulnerability against the short circuit. This thesis presents a new protection scheme for an SSSC in an MV network by using a varistor and thyristors to eliminate this weakness. The DC offset phenomenon is one of the main uncertainties that has been studied in the thesis. This phenomenon could cause a delay in the circuit breakers’ performance. In this thesis, the parameters of the machines that have most influence on the time when the fault current will pass the zero point have been analysed. Besides, the impact of the DC offset in the medium voltage network has been studied. Furthermore, the thermal issues have always been one of the most challenging problems for the power electronics devices. This thesis investigates a new packaging style by using the phase change material to improve the thermal managing of a press-pack thyristor during a short circuit. This packaging style is able to absorb the heat as much as required and also could decrease the thermal resistance

Management and Protection of High-Voltage Direct Current Systems Based on Modular Multilevel Converters

The electrical grid is undergoing large changes due to the massive integration of renewable energy systems and the electrification of transport and heating sectors. These new resources are typically non-dispatchable and dependent on external factors (e.g., weather, user patterns). These two aspects make the generation and demand less predictable, facilitating a larger power variability. As a consequence, rejecting disturbances and respecting power quality constraints gets more challenging, as small power imbalances can create large frequency deviations with faster transients. In order to deal with these challenges, the energy system needs an upgraded infrastructure and improved control system. In this regard, high-voltage direct current (HVdc) systems can increase the controllability of the power system, facilitating the integration of large renewable energy systems. This thesis contributes to the advancement of the state of the art in HVdc systems, addressing the modeling, control and protection of HVdc systems, adopting modular multilevel converter (MMC) technology, with focus in providing services to ac systems. HVdc system control and protection studies need for an accurate HVdc terminal modeling in largely different time frames. Thus, as a first step, this thesis presents a guideline for the necessary level of deepness of the power electronics modeling with respect to the power system problem under study. Starting from a proper modeling for power system studies, this thesis proposes an HVdc frequency regulation approach, which adapts the power consumption of voltage-dependent loads by means of controlled reactive power injections, that control the voltage in the grid. This solution enables a fast and accurate load power control, able to minimize the frequency swing in asynchronous or embedded HVdc applications. One key challenge of HVdc systems is a proper protection system and particularly dc circuit breaker (CB) design, which necessitates fault current analysis for a large number of grid scenarios and parameters. This thesis applies the knowledge developed in the modeling and control of HVdc systems, to develop a fast and accurate fault current estimation method for MMC-based HVdc system. This method, including the HVdc control, achieved to accurately estimate the fault current peak value and slope with very small computational effort compared to the conventional approach using EMT-simulations. This work is concluded introducing a new protection methodology, that involves the fault blocking capability of MMCs with mixed submodule (SM) structure, without the need for an additional CB. The main focus is the adaption of the MMC topology with reduced number of bipolar SM to achieve similar fault clearing performance as with dc CB and tolerable SM over-voltage

Protection of Future Electricity Systems

The electrical energy industry is undergoing dramatic changes: massive deployment of renewables, increasing share of DC networks at transmission and distribution levels, and at the same time, a continuing reduction in conventional synchronous generation, all contribute to a situation where a variety of technical and economic challenges emerge. As the society’s reliance on electrical power continues to increase as a result of international decarbonisation commitments, the need for secure and uninterrupted delivery of electrical energy to all customers has never been greater. Power system protection plays an important enabling role in future decarbonized energy systems. This book includes ten papers covering a wide range of topics related to protection system problems and solutions, such as adaptive protection, protection of HVDC and LVDC systems, unconventional or enhanced protection methods, protection of superconducting transmission cables, and high voltage lightning protection. This volume has been edited by Adam Dyśko, Senior Lecturer at the University of Strathclyde, UK, and Dimitrios Tzelepis, Research Fellow at the University of Strathclyde

Development of a current limiting solid-state circuit breaker based on wide-band gap power semiconductor devices for 400V DC microgrid protection

Popularity of DC distribution systems is increasing for many residential and industrial applications such as data centres, commercial and residential buildings, telecommunication systems, and transport power networks etc. Compared to AC systems, they have demonstrated higher power efficiency, less complexity, and more readiness of integrating with various local power sources and DC electronic loads. However, one of the major technical issues hindering this trend is the lack of effective DC fault protection devices/circuits. Although conventional electromechanical circuit breakers work well in AC systems, they are not suitable for DC systems due to their long response time (ranging from tens of milliseconds to hundreds of milliseconds). Such a long response time is far beyond the withstand time (typically tens of microseconds) of most power electronic devices in short-circuit operating conditions. In contrast, Solid-State Circuit Breakers (SSCBs) are able to offer ultrafast switching speed thanks to the modern power semiconductor devices which can turn off in microseconds or even in tens of nanoseconds. Furthermore, the ever-increasing fault current level in DC systems poses a significant mechanical and thermal stress on the whole DC system. Therefore, the desire for the protection devices with the feature of fast switching speed along with the current-limiting capability has prompted intensive research in this area over the last decade in both academia and industry. However, the relatively high conduction losses and limited short-circuit capability are two of the major drawbacks of SSCBs. With the growing maturity and increasingly commercial availability of Wide-Bandgap (WBG) semiconductor devices, a SSCB based-on WBG devices is a promising solution to alleviate the issues since WBG semiconductors have demonstrated superior material properties over the conventional silicon material such as lower specific on-resistance, higher junction temperatures and higher breakdown voltage. This research aims to design and develop a WBG-based solid-state circuit breaker for a 400V DC microgrid application. To accomplish this task, this work starts with a comprehensive review of DC microgrid technology followed by an extensive review of the state-of-the-art DC circuit breakers. Then, to develop a circuit topology for the proposed SSCB, a practical current limiter is analysed, simulated, and evaluated. Based on this topology, the proposed SSCB is configured with a high-voltage normally-on Silicon Carbide Junction Field Effect Transistors (SiC-JFETs) cascading a low-voltage normally-off power MOSFET. This solution offers several advantages. For example, it does not require any additional sensing and tripping circuitry for short-circuit protection and therefore has a fast response speed. Meanwhile, the use of power SiC JFETs tends to reduce the conduction losses and enhance the short-circuit robustness of SSCBs. In addition, it offers the feature of current limiting which could ease the thermal and mechanical stresses on the whole DC system. The operating process of the proposed SSCB is analysed and the analytical results are compared with the simulated results; In the end, a prototype SSCB has been built and evaluated for short-circuit protection in a 400V DC system. In addition, to effectively suppress the overvoltage at the turn-off of SSCBs, a novel hybrid snubber circuit has been proposed by taking into account the advantages offered by both conventional Resistor-Capacitor-Diode (RCD) snubbers and Metal-Oxide Varistors (MOVs). Finally, other functions of the proposed SSCBs including overload protection, over temperature protection and protection coordination have been investigated and some operating issues such as false tripping and SSCB reset have been addressed

Design and Implementation of High-Efficiency, Lightweight, System-Friendly Solid-State Circuit Breaker

Direct current (DC) distribution system has shown potential over the alternative current (AC) distribution system in some application scenarios, e.g., electrified transportation, renewable energy, data center, etc. Because of the fast response speed, DC solid-state circuit breaker (SSCB) becomes a promising technology for the future power electronics intensive DC energy system with fault-tolerant capability. First, a thorough literature survey is performed to review the DC-SSCB technology. The key components for DC-SSCB, including power semiconductors, topologies, energy absorption units, and fault detection circuits, are studied. It is observed that the prior studies mainly focus on the basic interruption capability of the DC-SSCB. There are not so many studies on SSCB’s size optimization or system-friendly functions. Second, an insulated gate bipolar transistor (IGBT) based lightweight SSCB is proposed. With the reduced gate voltage, the proposed SSCB can limit the peak fault current without the bulky and heavy fault current limiting the inductor, which exists in the conventional SSCB circuit. Thus, the specific power density of the SSCB is substantially improved compared with the conventional design. Meanwhile, to understand the impact of different design parameters on the performance of SSCB, an analytical model is built to establish the relationship between SSCB dynamic performance and operating conditions considering the key components and circuit parasitics. Simulation and test results demonstrate the accuracy of the proposed model. To limit the fault current with the proposed SSCB without a current limiting inductor, power semiconductors need to operate in the active region temporarily. During this interval, a severe voltage oscillation has been observed experimentally, leading to the DC-SSCB overstress and eventually the failure. A detailed MATLAB/Simulink model is built to understand the mechanism causing the voltage oscillation. Three suppression methods using enhanced gate drive circuitry are proposed and compared. Test results based on a 2kV/1kA SSCB prototype demonstrate the effectiveness of the proposed oscillation mitigation method and the accuracy of the derived model. Meanwhile, when the system fault impedance is close to zero (e.g., high di/dt), the influence of the parasitic inductance contributed by interconnection (e.g., bus bar, module package, etc.) cannot be neglected. To study the influence of the bus bar connections on SSCB with high di/dt, a Q3D extractor is adopted to extract the parasitic parameters of the SSCB and understand the influence of different bus bar connections. A vertical bus bar is proposed to suppress the side effect and verified by the Q3D extractor and experimental results. Finally, a system-friendly SSCB is demonstrated. The proposed gate drive enables the SSCB to operate in the current limitation mode for the overcurrent limitation. The current limitation level and limitation time can be tuned by the gate drive. Then, this dissertation provides an all-in-one solution with integrated circuitries as the fault detector, actuator for the semiconductor’s operating status regulation, and coordinated control. This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and also take different responses under different fault cases. The feasibility and the effectiveness of the proposed system-friendly SSCB are validated with experimental results based on a 200V/10A SSCB demonstrator

Methods and Results of Power Cycling Tests for Semiconductor Power Devices

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25

Design feasability of the electrical network for turboelectric aircraft propulsion.

The motivation for this research is the need for safer and more environmentally friendly air transport system. Electrical propulsion systems have been identified as a potential method for improving aircraft performance going forward. The implementation of electrical drive trains for future aircraft propulsion comes with many challenges, due to the novelty and scale of the intended deployments. Major technological advancements and research are ongoing at system and component level to meet this ambition. However, the feasibility aspects of these studies have focused more on the engine side than on the electrical aspects, especially with regards to system reliability and stability. These have been considered in the earlier proposed sizing methods, using assumed fault and transient current magnitudes. Such assumption implies that the control and protection systems, may not properly handle abnormal operational scenarios. The aim of this research is to establish a procedure for sizing components of an electric propulsion system considering reliability and stability. The major objective is to properly quantify the operating parameters in non-steady state operations, like transients and fault scenarios, and establish that components are operating within their thermal limits at all operational stages. The contribution of this work is the development of a method that incorporates stability and reliability in the sizing process of electrical propulsion networks. The practicality of the proposed methods has also been validated experimentally, using a test facility set up for this study. The impact of this work is the reduction of the design uncertainties, resulting from assumed fault and transient characteristics of an electrical propulsion system. The results show that the assumptions in earlier researches do not suffice for the investigated architectures. A considerable mass penalty is incurred, with the power electronic devices having to be sized for slightly higher than the maximum transient currents.PhD in Aerospac

Electromagnetic fast-transients in LV networks with ubiquitous small-scale embedded generation

Small-scale embedded generation projects rated below 16A per phase are being integrated into low-voltage distribution networks in ever increasing numbers. Seen from the network operator's perspective as little more than negative load, the commissioning of such generators is subject to compliance with the Fit and Forget connection requirements of ENA Engineering Recommendation G83/1. This thesis has sought to quantify the electromagnetic switching transient implications of integrating very large volumes of embedded generation into the UK's low-voltage supply networks. Laboratory testing of a converter-interfaced PV source has been undertaken to characterise typical switching transient waveshapes, and equivalent representative source models have been constructed in EMTP-ATP. A detailed frequency-dependent travelling wave equivalent of the DNO-approved Generic UK LV Distribution network model has been developed and, by means of extensive statistical simulation studies, used to quantify the cumulative impact of geographically localised generators switching in response to common network conditions. It is found that the magnitude of generator-induced voltage and current transients is dependent on the number of concurrently switched generators, and on their relative locations within the network. A theoretical maximum overvoltage of 1.72pu is predicted at customer nodes remote from the LV transformer terminals, for a scenario in which all households have installed embedded generation. Latent diversity in switch pole closing and inrush inception times is found to reduce predicted peak transient voltages to around 25-40% of their theoretical maxima.EThOS - Electronic Theses Online ServiceGBUnited Kingdo